AR
Publications
- Network on Chip for Consumer Electronics Devices: An Architectural and Performance Exploration of Synchronous and Asynchronous Network-on-Chip-Based Systems
- Parametric performance analysis of synchronous and asynchronous heterogeneous network on chip
- Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard
- Local Bit-Line Sharing Robust Dual-Port 8T SRAM With Virtual VSS for Energy-Efficient In-Memory Computing Architecture
- An Energy-Efficient Hybrid SRAM-Based In-Memory Computing Macro for Artificial Intelligence Edge Devices
- Local bitline 8T SRAM based in-memory computing architecture for energy-efficient linear error correction codec implementation
- A 0.32V Bit-Interleave 8T SRAM based In-Memory Computing Macro for AI Edge Devices
- An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor