FPGA implementation of pipelined architecture for optical imaging distortion correction

Fast and efficient operation is a major challenge for complex image processing algorithms executed in hardware. This paper describes novel algorithms for correcting optical geometric distortion in imaging systems, together with the architectures used to implement them in FPGA-based hardware. The proposed architecture produces a fast, almost real-time solution for the correction of image distortion implemented using VHDL HDL with a single Xilinx FPGA XCS3 1000-4 device. Using dedicated SRLC16 shift registers to build the synchronous FIFOs is an ideal utilization of the device resources available. The experimental results show that the barrel distortion can be quickly corrected with a very low residual error. The design can also be applied to other imaging processing algorithms in optical systems. ©2006 IEEE.