Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
mydac |
18 |
9 |
0 |
9 |
12 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
pll1|altpll_component|auto_generated |
2 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
pll1 |
1 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|dual_sync_internal |
4 |
0 |
2 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|conduit_splitter_internal |
3 |
0 |
2 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|adc_inst|adcblock_instance |
9 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|adc_inst|decoder |
5 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|adc_inst |
9 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|FIFOram |
28 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo |
16 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated |
16 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|u_control_fsm|ts_avrg_fifo |
16 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|u_control_fsm |
26 |
0 |
0 |
0 |
30 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2 |
13 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|adc_inst|adcblock_instance |
9 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|adc_inst|decoder |
5 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|adc_inst |
9 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|FIFOram |
28 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo |
16 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated |
16 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|u_control_fsm|ts_avrg_fifo |
16 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|u_control_fsm |
26 |
0 |
0 |
0 |
30 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal |
13 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0 |
20 |
0 |
0 |
0 |
42 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc |
20 |
0 |
0 |
0 |
38 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |