Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
myfl|altsyncram_component|auto_generated|altsyncram1 |
8 |
0 |
2 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myfl|altsyncram_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myfl |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mydelay|altsyncram_component|auto_generated|altsyncram1 |
16 |
0 |
2 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mydelay|altsyncram_component|auto_generated |
8 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mydelay |
8 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myswitch|altsyncram_component|auto_generated|altsyncram1 |
8 |
0 |
2 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myswitch|altsyncram_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myswitch |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mymode|altsyncram_component|auto_generated|altsyncram1 |
8 |
0 |
2 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mymode|altsyncram_component|auto_generated |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mymode |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myK00|altsyncram_component|auto_generated|altsyncram1 |
42 |
0 |
2 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myK00|altsyncram_component|auto_generated |
21 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myK00 |
21 |
1 |
0 |
1 |
18 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
myprediction|altsyncram_component|auto_generated|altsyncram1|mux7 |
33 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myprediction|altsyncram_component|auto_generated|altsyncram1|mux6 |
33 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myprediction|altsyncram_component|auto_generated|altsyncram1|rden_decode_b |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myprediction|altsyncram_component|auto_generated|altsyncram1|rden_decode_a |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myprediction|altsyncram_component|auto_generated|altsyncram1|decode5 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myprediction|altsyncram_component|auto_generated|altsyncram1|decode4 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myprediction|altsyncram_component|auto_generated|altsyncram1 |
64 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myprediction|altsyncram_component|auto_generated |
32 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myprediction |
32 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
mycontrol_perturbation|altsyncram_component|auto_generated|altsyncram1|mux7 |
33 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mycontrol_perturbation|altsyncram_component|auto_generated|altsyncram1|mux6 |
33 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mycontrol_perturbation|altsyncram_component|auto_generated|altsyncram1|rden_decode_b |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mycontrol_perturbation|altsyncram_component|auto_generated|altsyncram1|rden_decode_a |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mycontrol_perturbation|altsyncram_component|auto_generated|altsyncram1|decode5 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mycontrol_perturbation|altsyncram_component|auto_generated|altsyncram1|decode4 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mycontrol_perturbation|altsyncram_component|auto_generated|altsyncram1 |
64 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mycontrol_perturbation|altsyncram_component|auto_generated |
32 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mycontrol_perturbation |
32 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
mydesired_V1_out|altsyncram_component|auto_generated|altsyncram1|mux7 |
33 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mydesired_V1_out|altsyncram_component|auto_generated|altsyncram1|mux6 |
33 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mydesired_V1_out|altsyncram_component|auto_generated|altsyncram1|rden_decode_b |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mydesired_V1_out|altsyncram_component|auto_generated|altsyncram1|rden_decode_a |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mydesired_V1_out|altsyncram_component|auto_generated|altsyncram1|decode5 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mydesired_V1_out|altsyncram_component|auto_generated|altsyncram1|decode4 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mydesired_V1_out|altsyncram_component|auto_generated|altsyncram1 |
64 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mydesired_V1_out|altsyncram_component|auto_generated |
32 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mydesired_V1_out |
32 |
16 |
0 |
16 |
16 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
myadc_2_ram|altsyncram_component|auto_generated|altsyncram1|mux7 |
25 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myadc_2_ram|altsyncram_component|auto_generated|altsyncram1|mux6 |
25 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myadc_2_ram|altsyncram_component|auto_generated|altsyncram1|rden_decode_b |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myadc_2_ram|altsyncram_component|auto_generated|altsyncram1|rden_decode_a |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myadc_2_ram|altsyncram_component|auto_generated|altsyncram1|decode5 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myadc_2_ram|altsyncram_component|auto_generated|altsyncram1|decode4 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myadc_2_ram|altsyncram_component|auto_generated|altsyncram1 |
56 |
0 |
0 |
0 |
24 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myadc_2_ram|altsyncram_component|auto_generated |
28 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myadc_2_ram |
28 |
12 |
0 |
12 |
12 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
myadc_1_ram|altsyncram_component|auto_generated|altsyncram1|mux7 |
25 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myadc_1_ram|altsyncram_component|auto_generated|altsyncram1|mux6 |
25 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myadc_1_ram|altsyncram_component|auto_generated|altsyncram1|rden_decode_b |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myadc_1_ram|altsyncram_component|auto_generated|altsyncram1|rden_decode_a |
1 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myadc_1_ram|altsyncram_component|auto_generated|altsyncram1|decode5 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myadc_1_ram|altsyncram_component|auto_generated|altsyncram1|decode4 |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myadc_1_ram|altsyncram_component|auto_generated|altsyncram1 |
56 |
0 |
0 |
0 |
24 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myadc_1_ram|altsyncram_component|auto_generated |
28 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
myadc_1_ram |
28 |
12 |
0 |
12 |
12 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
my_u_train_test|altsyncram_component|auto_generated|altsyncram1 |
60 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_u_train_test|altsyncram_component|auto_generated |
30 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_u_train_test |
30 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mydesired_V1|altsyncram_component|auto_generated|altsyncram1 |
62 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mydesired_V1|altsyncram_component|auto_generated |
31 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mydesired_V1 |
31 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
mydac |
18 |
9 |
0 |
9 |
12 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
pll1|altpll_component|auto_generated |
2 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
pll1 |
1 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|dual_sync_internal |
4 |
0 |
2 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|conduit_splitter_internal |
3 |
0 |
2 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|adc_inst|adcblock_instance |
9 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|adc_inst|decoder |
5 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|adc_inst |
9 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|FIFOram |
28 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo |
16 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated |
16 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|u_control_fsm|ts_avrg_fifo |
16 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2|u_control_fsm |
26 |
0 |
0 |
0 |
30 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal_2 |
13 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|adc_inst|adcblock_instance |
9 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|adc_inst|decoder |
5 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|adc_inst |
9 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|FIFOram |
28 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated|dpfifo |
16 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|u_control_fsm|ts_avrg_fifo|scfifo_component|auto_generated |
16 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|u_control_fsm|ts_avrg_fifo |
16 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal|u_control_fsm |
26 |
0 |
0 |
0 |
30 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0|control_internal |
13 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc|modular_dual_adc_0 |
20 |
0 |
0 |
0 |
42 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
my_dual_adc |
20 |
0 |
0 |
0 |
38 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |