modular_dual_adc_0
altera_modular_dual_adc v21.1
Parameters
CORE_VAR |
3 |
ENABLE_DEBUG |
0 |
MONITOR_COUNT_WIDTH |
12 |
CLOCK_FREQ |
0 |
FAMILY |
MAX10FPGA |
DEVICE_PART |
10M50DAF484C6GES |
device_partname_fivechar_prefix |
10M50 |
device_adc_type |
33 |
max_adc_count_on_die |
2 |
adc_count_on_device |
2 |
device_power_supply_type |
2 |
analog_input_pin_mask |
0 |
analog_input_pin_mask_adc2 |
0 |
hard_pwd |
0 |
sample_rate |
0 |
clkdiv |
5 |
derived_clkdiv |
5 |
tsclkdiv |
1 |
tsclksel |
1 |
refsel |
1 |
external_vref |
2.5 |
int_vref_vr |
3.0 |
int_vref_nonvr |
2.5 |
reference_voltage |
2.5 |
prescalar |
0 |
reference_voltage_sim |
65536 |
refsel_adc2 |
1 |
external_vref_adc2 |
2.5 |
int_vref_vr_adc2 |
3.0 |
int_vref_nonvr_adc2 |
2.5 |
reference_voltage_adc2 |
2.5 |
prescalar_adc2 |
0 |
reference_voltage_sim_adc2 |
65536 |
enable_usr_sim |
0 |
use_tsd |
false |
en_tsd_max |
false |
tsd_max |
125 |
en_tsd_min |
false |
tsd_min |
0 |
use_ch0 |
true |
en_thmax_ch0 |
false |
thmax_ch0 |
0.0 |
en_thmin_ch0 |
false |
thmin_ch0 |
0.0 |
simfilename_ch0 |
|
use_ch1 |
false |
en_thmax_ch1 |
false |
thmax_ch1 |
0.0 |
en_thmin_ch1 |
false |
thmin_ch1 |
0.0 |
simfilename_ch1 |
|
use_ch2 |
false |
en_thmax_ch2 |
false |
thmax_ch2 |
0.0 |
en_thmin_ch2 |
false |
thmin_ch2 |
0.0 |
simfilename_ch2 |
|
use_ch3 |
false |
en_thmax_ch3 |
false |
thmax_ch3 |
0.0 |
en_thmin_ch3 |
false |
thmin_ch3 |
0.0 |
simfilename_ch3 |
|
use_ch4 |
false |
en_thmax_ch4 |
false |
thmax_ch4 |
0.0 |
en_thmin_ch4 |
false |
thmin_ch4 |
0.0 |
simfilename_ch4 |
|
use_ch5 |
false |
en_thmax_ch5 |
false |
thmax_ch5 |
0.0 |
en_thmin_ch5 |
false |
thmin_ch5 |
0.0 |
simfilename_ch5 |
|
use_ch6 |
false |
en_thmax_ch6 |
false |
thmax_ch6 |
0.0 |
en_thmin_ch6 |
false |
thmin_ch6 |
0.0 |
simfilename_ch6 |
|
use_ch7 |
false |
en_thmax_ch7 |
false |
thmax_ch7 |
0.0 |
en_thmin_ch7 |
false |
thmin_ch7 |
0.0 |
simfilename_ch7 |
|
use_ch8 |
false |
prescaler_ch8 |
false |
en_thmax_ch8 |
false |
thmax_ch8 |
0.0 |
en_thmin_ch8 |
false |
thmin_ch8 |
0.0 |
simfilename_ch8 |
|
use_ch9 |
true |
en_thmax_ch9 |
false |
thmax_ch9 |
0.0 |
en_thmin_ch9 |
false |
thmin_ch9 |
0.0 |
simfilename_ch9 |
|
use_ch10 |
false |
en_thmax_ch10 |
false |
thmax_ch10 |
0.0 |
en_thmin_ch10 |
false |
thmin_ch10 |
0.0 |
simfilename_ch10 |
|
use_ch11 |
false |
en_thmax_ch11 |
false |
thmax_ch11 |
0.0 |
en_thmin_ch11 |
false |
thmin_ch11 |
0.0 |
simfilename_ch11 |
|
use_ch12 |
false |
en_thmax_ch12 |
false |
thmax_ch12 |
0.0 |
en_thmin_ch12 |
false |
thmin_ch12 |
0.0 |
simfilename_ch12 |
|
use_ch13 |
false |
en_thmax_ch13 |
false |
thmax_ch13 |
0.0 |
en_thmin_ch13 |
false |
thmin_ch13 |
0.0 |
simfilename_ch13 |
|
use_ch14 |
false |
en_thmax_ch14 |
false |
thmax_ch14 |
0.0 |
en_thmin_ch14 |
false |
thmin_ch14 |
0.0 |
simfilename_ch14 |
|
use_ch15 |
false |
en_thmax_ch15 |
false |
thmax_ch15 |
0.0 |
en_thmin_ch15 |
false |
thmin_ch15 |
0.0 |
simfilename_ch15 |
|
use_ch16 |
false |
en_thmax_ch16 |
false |
thmax_ch16 |
0.0 |
en_thmin_ch16 |
false |
thmin_ch16 |
0.0 |
simfilename_ch16 |
|
use_ch17 |
false |
prescaler_ch17 |
false |
en_thmax_ch17 |
false |
thmax_ch17 |
0.0 |
en_thmin_ch17 |
false |
thmin_ch17 |
0.0 |
simfilename_ch17 |
|
seq_order_length |
1 |
seq_order_slot_1 |
30 |
seq_order_slot_2 |
30 |
seq_order_slot_3 |
30 |
seq_order_slot_4 |
30 |
seq_order_slot_5 |
30 |
seq_order_slot_6 |
30 |
seq_order_slot_7 |
30 |
seq_order_slot_8 |
30 |
seq_order_slot_9 |
30 |
seq_order_slot_10 |
30 |
seq_order_slot_11 |
30 |
seq_order_slot_12 |
30 |
seq_order_slot_13 |
30 |
seq_order_slot_14 |
30 |
seq_order_slot_15 |
30 |
seq_order_slot_16 |
30 |
seq_order_slot_17 |
30 |
seq_order_slot_18 |
30 |
seq_order_slot_19 |
30 |
seq_order_slot_20 |
30 |
seq_order_slot_21 |
30 |
seq_order_slot_22 |
30 |
seq_order_slot_23 |
30 |
seq_order_slot_24 |
30 |
seq_order_slot_25 |
30 |
seq_order_slot_26 |
30 |
seq_order_slot_27 |
30 |
seq_order_slot_28 |
30 |
seq_order_slot_29 |
30 |
seq_order_slot_30 |
30 |
seq_order_slot_31 |
30 |
seq_order_slot_32 |
30 |
seq_order_slot_33 |
30 |
seq_order_slot_34 |
30 |
seq_order_slot_35 |
30 |
seq_order_slot_36 |
30 |
seq_order_slot_37 |
30 |
seq_order_slot_38 |
30 |
seq_order_slot_39 |
30 |
seq_order_slot_40 |
30 |
seq_order_slot_41 |
30 |
seq_order_slot_42 |
30 |
seq_order_slot_43 |
30 |
seq_order_slot_44 |
30 |
seq_order_slot_45 |
30 |
seq_order_slot_46 |
30 |
seq_order_slot_47 |
30 |
seq_order_slot_48 |
30 |
seq_order_slot_49 |
30 |
seq_order_slot_50 |
30 |
seq_order_slot_51 |
30 |
seq_order_slot_52 |
30 |
seq_order_slot_53 |
30 |
seq_order_slot_54 |
30 |
seq_order_slot_55 |
30 |
seq_order_slot_56 |
30 |
seq_order_slot_57 |
30 |
seq_order_slot_58 |
30 |
seq_order_slot_59 |
30 |
seq_order_slot_60 |
30 |
seq_order_slot_61 |
30 |
seq_order_slot_62 |
30 |
seq_order_slot_63 |
30 |
seq_order_slot_64 |
30 |
seq_order_slot_1_adc2 |
30 |
seq_order_slot_2_adc2 |
30 |
seq_order_slot_3_adc2 |
30 |
seq_order_slot_4_adc2 |
30 |
seq_order_slot_5_adc2 |
30 |
seq_order_slot_6_adc2 |
30 |
seq_order_slot_7_adc2 |
30 |
seq_order_slot_8_adc2 |
30 |
seq_order_slot_9_adc2 |
30 |
seq_order_slot_10_adc2 |
30 |
seq_order_slot_11_adc2 |
30 |
seq_order_slot_12_adc2 |
30 |
seq_order_slot_13_adc2 |
30 |
seq_order_slot_14_adc2 |
30 |
seq_order_slot_15_adc2 |
30 |
seq_order_slot_16_adc2 |
30 |
seq_order_slot_17_adc2 |
30 |
seq_order_slot_18_adc2 |
30 |
seq_order_slot_19_adc2 |
30 |
seq_order_slot_20_adc2 |
30 |
seq_order_slot_21_adc2 |
30 |
seq_order_slot_22_adc2 |
30 |
seq_order_slot_23_adc2 |
30 |
seq_order_slot_24_adc2 |
30 |
seq_order_slot_25_adc2 |
30 |
seq_order_slot_26_adc2 |
30 |
seq_order_slot_27_adc2 |
30 |
seq_order_slot_28_adc2 |
30 |
seq_order_slot_29_adc2 |
30 |
seq_order_slot_30_adc2 |
30 |
seq_order_slot_31_adc2 |
30 |
seq_order_slot_32_adc2 |
30 |
seq_order_slot_33_adc2 |
30 |
seq_order_slot_34_adc2 |
30 |
seq_order_slot_35_adc2 |
30 |
seq_order_slot_36_adc2 |
30 |
seq_order_slot_37_adc2 |
30 |
seq_order_slot_38_adc2 |
30 |
seq_order_slot_39_adc2 |
30 |
seq_order_slot_40_adc2 |
30 |
seq_order_slot_41_adc2 |
30 |
seq_order_slot_42_adc2 |
30 |
seq_order_slot_43_adc2 |
30 |
seq_order_slot_44_adc2 |
30 |
seq_order_slot_45_adc2 |
30 |
seq_order_slot_46_adc2 |
30 |
seq_order_slot_47_adc2 |
30 |
seq_order_slot_48_adc2 |
30 |
seq_order_slot_49_adc2 |
30 |
seq_order_slot_50_adc2 |
30 |
seq_order_slot_51_adc2 |
30 |
seq_order_slot_52_adc2 |
30 |
seq_order_slot_53_adc2 |
30 |
seq_order_slot_54_adc2 |
30 |
seq_order_slot_55_adc2 |
30 |
seq_order_slot_56_adc2 |
30 |
seq_order_slot_57_adc2 |
30 |
seq_order_slot_58_adc2 |
30 |
seq_order_slot_59_adc2 |
30 |
seq_order_slot_60_adc2 |
30 |
seq_order_slot_61_adc2 |
30 |
seq_order_slot_62_adc2 |
30 |
seq_order_slot_63_adc2 |
30 |
seq_order_slot_64_adc2 |
30 |
AUTO_DEVICE_SPEEDGRADE |
6 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |
|
Software Assignments
ADC1_PRESCALER_CH8 |
0 |
ADC1_REFSEL |
Internal VREF |
ADC1_USE_CH0 |
1 |
ADC1_USE_CH1 |
0 |
ADC1_USE_CH2 |
0 |
ADC1_USE_CH3 |
0 |
ADC1_USE_CH4 |
0 |
ADC1_USE_CH5 |
0 |
ADC1_USE_CH6 |
0 |
ADC1_USE_CH7 |
0 |
ADC1_USE_CH8 |
0 |
ADC1_USE_TSD |
0 |
ADC1_VREF |
2.5 |
ADC2_PRESCALER_CH8 |
0 |
ADC2_REFSEL |
Internal VREF |
ADC2_USE_CH0 |
1 |
ADC2_USE_CH1 |
0 |
ADC2_USE_CH2 |
0 |
ADC2_USE_CH3 |
0 |
ADC2_USE_CH4 |
0 |
ADC2_USE_CH5 |
0 |
ADC2_USE_CH6 |
0 |
ADC2_USE_CH7 |
0 |
ADC2_USE_CH8 |
0 |
ADC2_VREF |
2.5 |
CORE_VARIANT |
3 |
DUAL_ADC_MODE |
true |
|