alt_sld_fab

2023.09.27.14:33:09 Datasheet
Overview

Memory Map

alt_sld_fab

alt_sld_fab v21.1


Parameters

DESIGN_HASH 2386d159ae0e8b6cfc55
NODE_COUNT 10
MAX_WIDTH 31
SETTINGS {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 0 ir_width 8 psig 9b67919e} {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 1 ir_width 8 psig 9b67919e} {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 2 ir_width 8 psig 9b67919e} {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 3 ir_width 8 psig 9b67919e} {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 4 ir_width 8 psig 9b67919e} {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 5 ir_width 8 psig 9b67919e} {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 6 ir_width 8 psig 9b67919e} {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 7 ir_width 8 psig 9b67919e} {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 8 ir_width 8 psig 9b67919e} {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 9 ir_width 8 psig 9b67919e}
CLOCKS {id {} } {id {} } {id {} } {id {} } {id {} } {id {} } {id {} } {id {} } {id {} } {id {} }
AGENTS
EP_INFOS {hpath {desired_V1:mydesired_V1|altsyncram:altsyncram_component|altsyncram_dti1:auto_generated|sld_mod_ram_rom:mgl_prim2} } {hpath {u_train_test:my_u_train_test|altsyncram:altsyncram_component|altsyncram_1vi1:auto_generated|sld_mod_ram_rom:mgl_prim2} } {hpath {adc_1_ram:myadc_1_ram|altsyncram:altsyncram_component|altsyncram_jgg1:auto_generated|sld_mod_ram_rom:mgl_prim2} } {hpath {adc_2_ram:myadc_2_ram|altsyncram:altsyncram_component|altsyncram_kgg1:auto_generated|sld_mod_ram_rom:mgl_prim2} } {hpath {desired_V1_out:mydesired_V1_out|altsyncram:altsyncram_component|altsyncram_ohg1:auto_generated|sld_mod_ram_rom:mgl_prim2} } {hpath {control_perturbation:mycontrol_perturbation|altsyncram:altsyncram_component|altsyncram_jjg1:auto_generated|sld_mod_ram_rom:mgl_prim2} } {hpath {prediction:myprediction|altsyncram:altsyncram_component|altsyncram_9jg1:auto_generated|sld_mod_ram_rom:mgl_prim2} } {hpath {K00:myK00|altsyncram:altsyncram_component|altsyncram_qoh1:auto_generated|sld_mod_ram_rom:mgl_prim2} } {hpath {mode:mymode|altsyncram:altsyncram_component|altsyncram_j9g1:auto_generated|sld_mod_ram_rom:mgl_prim2} } {hpath {switch:myswitch|altsyncram:altsyncram_component|altsyncram_o3g1:auto_generated|sld_mod_ram_rom:mgl_prim2} }
MIRROR 0
TOP_HUB 1
COMPOSED_SETTINGS {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 0 ir_width 8 bridge_agent 0 prefer_host {} } {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 1 ir_width 8 bridge_agent 0 prefer_host {} } {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 2 ir_width 8 bridge_agent 0 prefer_host {} } {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 3 ir_width 8 bridge_agent 0 prefer_host {} } {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 4 ir_width 8 bridge_agent 0 prefer_host {} } {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 5 ir_width 8 bridge_agent 0 prefer_host {} } {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 6 ir_width 8 bridge_agent 0 prefer_host {} } {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 7 ir_width 8 bridge_agent 0 prefer_host {} } {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 8 ir_width 8 bridge_agent 0 prefer_host {} } {fabric sld dir agent mfr_code 110 type_code 3 version 2 instance 9 ir_width 8 bridge_agent 0 prefer_host {} }
DEVICE_FAMILY MAX10FPGA
AUTO_DEVICE Unknown
AUTO_DEVICE_SPEEDGRADE Unknown
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_presplit

altera_super_splitter v21.1


Parameters

MAX_WIDTH 31
SEND_WIDTHS 10 10 10 10 10 10 10 10 10 10
RECEIVE_WIDTHS 31 31 31 31 31 31 31 31 31 31
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_splitter

altera_sld_splitter v21.1
alt_sld_fab_presplit pass   alt_sld_fab_splitter
  nodes
alt_sld_fab_sldfabric clock_0  
  clock_0
node_0  
  node_0
clock_1  
  clock_1
node_1  
  node_1
clock_2  
  clock_2
node_2  
  node_2
clock_3  
  clock_3
node_3  
  node_3
clock_4  
  clock_4
node_4  
  node_4
clock_5  
  clock_5
node_5  
  node_5
clock_6  
  clock_6
node_6  
  node_6
clock_7  
  clock_7
node_7  
  node_7
clock_8  
  clock_8
node_8  
  node_8
clock_9  
  clock_9
node_9  
  node_9


Parameters

FRAGMENTS {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 8 23} {irq irq out 1 1} {ir_out ir_out out 8 2} } clock clock assign {debug.controlledBy {link_0} } moduleassign {debug.virtualInterface.link_0 {debug.endpointLink {fabric sld index 1} } } } } {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 8 23} {irq irq out 1 1} {ir_out ir_out out 8 2} } clock clock assign {debug.controlledBy {link_1} } moduleassign {debug.virtualInterface.link_1 {debug.endpointLink {fabric sld index 2} } } } } {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 8 23} {irq irq out 1 1} {ir_out ir_out out 8 2} } clock clock assign {debug.controlledBy {link_2} } moduleassign {debug.virtualInterface.link_2 {debug.endpointLink {fabric sld index 3} } } } } {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 8 23} {irq irq out 1 1} {ir_out ir_out out 8 2} } clock clock assign {debug.controlledBy {link_3} } moduleassign {debug.virtualInterface.link_3 {debug.endpointLink {fabric sld index 4} } } } } {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 8 23} {irq irq out 1 1} {ir_out ir_out out 8 2} } clock clock assign {debug.controlledBy {link_4} } moduleassign {debug.virtualInterface.link_4 {debug.endpointLink {fabric sld index 5} } } } } {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 8 23} {irq irq out 1 1} {ir_out ir_out out 8 2} } clock clock assign {debug.controlledBy {link_5} } moduleassign {debug.virtualInterface.link_5 {debug.endpointLink {fabric sld index 6} } } } } {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 8 23} {irq irq out 1 1} {ir_out ir_out out 8 2} } clock clock assign {debug.controlledBy {link_6} } moduleassign {debug.virtualInterface.link_6 {debug.endpointLink {fabric sld index 7} } } } } {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 8 23} {irq irq out 1 1} {ir_out ir_out out 8 2} } clock clock assign {debug.controlledBy {link_7} } moduleassign {debug.virtualInterface.link_7 {debug.endpointLink {fabric sld index 8} } } } } {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 8 23} {irq irq out 1 1} {ir_out ir_out out 8 2} } clock clock assign {debug.controlledBy {link_8} } moduleassign {debug.virtualInterface.link_8 {debug.endpointLink {fabric sld index 9} } } } } {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 8 23} {irq irq out 1 1} {ir_out ir_out out 8 2} } clock clock assign {debug.controlledBy {link_9} } moduleassign {debug.virtualInterface.link_9 {debug.endpointLink {fabric sld index 10} } } } }
EXAMPLE
ADD_INTERFACE_ASGN 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_jtagpins

altera_jtag_pins_bridge v21.1


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_sldfabric

altera_sld_jtag_hub v21.1
alt_sld_fab_jtagpins clock   alt_sld_fab_sldfabric
  clock
node  
  node
clock_0   alt_sld_fab_splitter
  clock_0
node_0  
  node_0
clock_1  
  clock_1
node_1  
  node_1
clock_2  
  clock_2
node_2  
  node_2
clock_3  
  clock_3
node_3  
  node_3
clock_4  
  clock_4
node_4  
  node_4
clock_5  
  clock_5
node_5  
  node_5
clock_6  
  clock_6
node_6  
  node_6
clock_7  
  clock_7
node_7  
  node_7
clock_8  
  clock_8
node_8  
  node_8
clock_9  
  clock_9
node_9  
  node_9
ident   alt_sld_fab_ident
  ident_0


Parameters

DEVICE_FAMILY MAX10FPGA
SETTINGS {mfr_code 110 type_code 3 version 2 instance 0 ir_width 8 bridge_agent 0 prefer_host {} } {mfr_code 110 type_code 3 version 2 instance 1 ir_width 8 bridge_agent 0 prefer_host {} } {mfr_code 110 type_code 3 version 2 instance 2 ir_width 8 bridge_agent 0 prefer_host {} } {mfr_code 110 type_code 3 version 2 instance 3 ir_width 8 bridge_agent 0 prefer_host {} } {mfr_code 110 type_code 3 version 2 instance 4 ir_width 8 bridge_agent 0 prefer_host {} } {mfr_code 110 type_code 3 version 2 instance 5 ir_width 8 bridge_agent 0 prefer_host {} } {mfr_code 110 type_code 3 version 2 instance 6 ir_width 8 bridge_agent 0 prefer_host {} } {mfr_code 110 type_code 3 version 2 instance 7 ir_width 8 bridge_agent 0 prefer_host {} } {mfr_code 110 type_code 3 version 2 instance 8 ir_width 8 bridge_agent 0 prefer_host {} } {mfr_code 110 type_code 3 version 2 instance 9 ir_width 8 bridge_agent 0 prefer_host {} }
COUNT 10
N_SEL_BITS 4
N_NODE_IR_BITS 8
NODE_INFO 00010000000110000110111000001001000100000001100001101110000010000001000000011000011011100000011100010000000110000110111000000110000100000001100001101110000001010001000000011000011011100000010000010000000110000110111000000011000100000001100001101110000000100001000000011000011011100000000100010000000110000110111000000000
COMPILATION_MODE 0
BROADCAST_FEATURE 1
FORCE_IR_CAPTURE_FEATURE 1
FORCE_PRE_1_4_FEATURE 0
NEGEDGE_TDO_LATCH 1
ENABLE_SOFT_CORE_CONTROLLER 0
TOP_HUB 1
CONN_INDEX 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_ident

altera_connection_identification_hub v21.1
alt_sld_fab_sldfabric ident   alt_sld_fab_ident
  ident_0


Parameters

DESIGN_HASH 2386d159ae0e8b6cfc55
COUNT 1
SETTINGS {width 4 latency 0}
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
generation took 0.01 seconds rendering took 0.03 seconds