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TOWARDS ENERGY-EFFICIENT EDGE SYSTEMS: THROUGH IN-SENSOR AND IN-MEMORY COMPUTING

thesis
posted on 2025-08-01, 15:58 authored by Gaurav KumarGaurav Kumar
<p dir="ltr">The surge in connected devices and data generation has propelled edge computing to the forefront of technological advancement. This thesis explores novel circuit- and system-level approaches to mitigate the challenges of edge computing, with a particular focus on low-power data compression at the point of sensing and energy-efficient in-memory computing (IMC) for machine learning (ML) inference at the network edge.<br>Traditional cloud-centric architectures suffer from persistent limitations, including bandwidth bottlenecks, high communication latency, and constrained energy budgets, particularly in resource-limited edge devices. Edge computing addresses these limitations by decentralizing computation, reducing dependence on cloud-based processing, improving real-time responsiveness, and enhancing data privacy.<br>This dissertation proposes four innovative approaches: (1) CS-Audio, a low-power compressive sensing–based audio codec for edge platforms, achieving 3×–15× data reduction and over 40× lower power than MP3; (2) d-AJC, an analog-domain MJPEG compressor leveraging switched-capacitor 2D-DCT and sparse-aware ADC, enabling in-sensor video compression with over 2× power and 20× ADC energy savings; (3) Ferroelectric CiM, a low-latency, energy-efficient IMC architecture using FeCap and FeFET devices, with software based training-time compensation and hardware-based circuit schemes to address low on/off ratio limitations; and (4) FP8-CiM, a hybrid floating-point CiM macro that combines Digital CiM for exponent and Analog CiM for mantissa MAC, enabling pipelined, scaling-free, and low-power FP8 inference for advanced ML workload<br>Collectively, these contributions advance the state of energy-efficient edge systems by addressing key bottlenecks across sensing, compression, and inference. The proposed techniques demonstrate the potential of integrated analog–digital hardware co-design for scalable, low-power intelligent edge platforms.</p>

Funding

Quasistatics Inc

CoCoSys

C-BRIC

SRC

History

Degree Type

  • Doctor of Philosophy

Department

  • Electrical and Computer Engineering

Campus location

  • West Lafayette

Advisor/Supervisor/Committee Chair

Kaushik Roy

Additional Committee Member 2

Anand Raghunathan

Additional Committee Member 3

Dimitrios Peroulis

Additional Committee Member 4

Vijay Raghunathan