Junction temperature characterisation of GaAs and GaN high electron mobility transistors
Thermal modelling of transistors becomes more accessible to circuit design engineers if the focus is shifted to the impact of heat on device terminal characteristics, instead of analysing the physics of nanoscale channel heat sources. This dissertation presents the gate junction temperature, rather than the peak channel temperature, as the dependable parameter for modelling the effect of temperature on device terminal characteristics. It is also argued that the gate junction temperature is crucial for modelling thermal degradation in GaAs and GaN devices.
An on-wafer electrical thermometry technique [gate metal resistance thermometry (GMRT)] is used in combination with template-based 3-D finite-element-method (FEM) thermal simulations to characterise GaAs and GaN HEMT gate junction temperature. Together they form an accurate thermal analysis procedure that is suitable for integration into an engineering design/work flow.
The impact of device operating conditions on GMRT is investigated, revealing the effect of gate leakage. Measurements and simulations of devices at constant power dissipation reveal that the bias dependence of the channel heat source profile affects the gate junction temperature.
Thermal parameter extraction procedures for GaAs and GaN device FEM thermal models are developed by assessing the effect of device structures/regions and the impact of bias state. Accurate thermal modelling can then be applied in reliability studies, and also integrated into design flows to meet performance specifications by optimising layout space and design margin.