Transient Stability of Paralleled Virtual Synchronous Generator and Grid-Following Inverter

The majority of inverter-based resources (IBRs) currently operate as grid-following inverters (GFLIs). However, these inverters exhibit certain stability issues when integrated in low-strength areas of the grid. To enhance the grid strength in a GFLI-dominant area, virtual synchronous generators (VSGs) can be installed. If the VSG and the GFLI are investigated as a paralleled system, despite the benefits brought by the VSG, in some cases, the transient angle instability process, caused by a voltage sag, is accelerated, making the whole system more prone to instability. Therefore, this paper aims to study the transient angle stability of a paralleled VSG-GFLI system via investigating the voltage at a common bus between the two IBRs. Subsequently, a stable region of the voltage angles of the two IBRs is determined. Based on this stable region, the stability margin of the paralleled system can be determined and used to quantitatively evaluate the system stability. Moreover, an additional control loop is proposed to improve the transient stability of the paralleled system in this paper. The proposed controller can adaptively reduce the power set-point of the VSG to avoid a complete failure of the VSG even when no stable equilibrium point exists during a voltage sag. The stability investigation and performance evaluation of the proposed method are conducted in PSCAD/EMTDC and experimentally validated.

Abstract-The majority of inverter-based resources (IBRs) currently operate as grid-following inverters (GFLIs).However, these inverters exhibit certain stability issues when integrated in low-strength areas of the grid.To enhance the grid strength in a GFLI-dominant area, virtual synchronous generators (VSGs) can be installed.If the VSG and the GFLI are investigated as a paralleled system, despite the benefits brought by the VSG, in some cases, the transient angle instability process, caused by a voltage sag, is accelerated, making the whole system more prone to instability.Therefore, this paper aims to study the transient angle stability of a paralleled VSG-GFLI system via investigating the voltage at a common bus between the two IBRs.Subsequently, a stable region of the voltage angles of the two IBRs is determined.Based on this stable region, the stability margin of the paralleled system can be determined and used to quantitatively evaluate the system stability.Moreover, an additional control loop is proposed to improve the transient stability of the paralleled system in this paper.The proposed controller can adaptively reduce the power set-point of the VSG to avoid a complete failure of the VSG even when no stable equilibrium point exists during a voltage sag.The stability investigation and performance evaluation of the proposed method are conducted in PSCAD/EMTDC and experimentally validated.
Index Terms-Angle Stability, Grid-following Inverter, Gridforming Inverter, Transient Stability, Virtual Synchronous Generator.Angle of the infinite bus voltage with respect to the angle reference at the common bus Z 1

NOMENCLATURE
Transmission line impedance between the VSG and the common bus Z 3 Transmission line impedance between the GFLI and the common bus Z g Transmission line impedance between the infinite bus and the common bus Current injected by the VSG I 3 Current injected by the GFLI I g Current injected from the infinite bus ω 0 Nominal frequency in rad/s ω Internal frequency of an IBR in rad/s P 0 Reference active power of the VSG Q 0 Reference reactive power of the VSG T HE majority of inverter-based resources (IBRs) employ grid-following inverters (GFLIs) to inject the generated energy to the grid.This type of inverter requires synchronizing units, e.g., phase-locked loops (PLLs), to follow the grid voltage [1].Increasingly, these IBRs are located in remote regions and distant from synchronous generators (SGs) [2].Thus, the frequency and voltage stability of GFLI-dominated areas are degraded due to a lack of rotational inertia and the deteriorated performance of conventional PLLs in weak grids [3], [4].Therefore, virtual synchronous generators (VSGs) are installed in these areas to improve the grid strength and provide virtual inertia and frequency support [5].Due to the promising applications of paralleled VSG-GFLI systems in weak grids, their stability should be investigated.
The small-signal stability of VSGs and GFLIs has been well investigated in the literature [6]- [9].As these IBRs are more vulnerable in voltage sag events, their transient stability (TS) during these large-signal disturbances has attracted significant attention recently [3], [10]- [24].A TS analysis studies the existence of stable equilibrium points (SEPs) after large-signal disturbances, e.g., faults.This analysis can also evaluate the stability margin of a system by investigating the stable region of the power angles.The TS analysis helps in designing systems that are robust against large-signal disturbances.
Various studies on the TS of a single GFLI have been conducted in the literature.The studies in [10], [11] provide insights into the loss of synchronization (LOS) mechanism of GFLIs under voltage sag events.Besides, the Lyapunov's direct method is utilized in [3] to evaluate the domain of attraction of the SEPs after a voltage sag.Additionally, various TS analysis methods for GFLIs are summarized in [12], [13].Moreover, the necessity of reactive current injection during faults is discussed in [11], [20].
In addition, TS of VSGs has been investigated in several works.The LOS of VSGs is discussed in [14]- [16], [18], [19], [22].When an SEP exists, a LOS might occur due to high virtual inertia and insufficient damping on the power angle [14], [15], [19].Impacts of the virtual inertia, damping factor, and virtual resistance on the TS of VSGs are demonstrated by the phase portrait analysis in [15] and [21], and studied by the Lyapunov's direct method in [16].These methods require doing forward integration and re-calculations in every iteration.Hence, they might lead to a high computational burden, especially if the complexity of the system grows.It is also shown that a current limiter can negatively impact the TS of a VSG [22].Moreover, the conventional reactive power loop reduces the active power limit of a VSG, hence, it is necessary to consider this loop in a TS analysis [22].To avoid a LOS, in [16], [19], [23], [24], various solutions have been proposed to enhance the system damping and support the internal voltage of the VSGs.However, these methods do not consider the cases without an SEP.To prevent a LOS when no SEP exists, [18] proposes a mode switching method that keeps the angle of VSG operating point (OP) around 90 • .However, keeping the VSG angle at 90 • might negatively impact the system voltage, hence degrading the stability of nearby IBRs.
All above studies are applied to solely VSGs or GFLIs, and the interactions between these two IBR types are rarely discussed.In [17], the negative impacts of active current injections from GFLIs on the TS of VSGs are revealed.However, the TS of the GFLI is not thoroughly discussed in [17].The discussions in [17] do not provide insights into the stability margin of the whole paralleled VSG-GFLI system.Additionally, in [25], the impact of a GFLI on the maximum allowable power angle of a parallel SG is quantitatively revealed.The study in [25] is applicable for a paralleled VSG-GFLI system.However, in [25], the stable condition of PLLs is simplified [11].In addition, while the internal voltage drop of the VSG due to the Q-V droop setting is a problematic issue as elaborated in [24], it is not considered in the SG-GFLI system in [25].The work in [26] also studies TS of SG-GFLI systems.The whole paralleled system in [26] forms a complete single-machine-infinite-bus (SMIB) system, without being connected to an external grid.Thus, this study does not show the impacts of low-strength connection conditions on the TS of the paralleled SG-GFLI systems and might not be applicable to the cases where VSG is installed to support a GFLI in a remote area of the network.Besides, taking both VSG and GFLI into consideration results in a fourthorder system, making the application of the phase portrait analysis impossible.Additionally, it is difficult to apply the Lyapunov's direct method to study the TS of a fourth-order system.Moreover, due to the energy dissipation of the VSG damping, this method is conservative [27].
To fill the gap of TS study for a paralleled VSG-GFLI system, a TS analysis for this paralleled system is conducted in this paper.It is shown that an excessive angle evolution of a VSG due to voltage sags might accelerate the transient instability process of a nearby GFLI.Additionally, the study in this paper allows quantitatively evaluating the TS of the paralleled VSG-GFLI system.Particularly, an expression of the voltage at a common bus between the VSG and the GFLI with respect to the angle of the IBRs is first derived.Based on the common bus voltage analysis and the dispatch levels of the two IBRs, the stability boundaries and margin of the paralleled system are obtained.This stability margin enables TS comparisons between different systems.As this analysis does not require doing forward integration or solving differential equations, it is promising to be scaled up for

TS study APRC
Determine stability boundaries of the VSG-GFLI system.

Adaptive operation:
• With SEP: Improve damping of the P − f loop, allow reference power to be tracked.
• Without SEP: Create a new SEP.
Determine stability margin of the VSG-GFLI system.
Designed to keep the OP of the paralleled system away from the stability boundaries.analysing TS of a multiple-IBR system.The study on multiple-IBR network is a continuation of this work.
From the analysis mentioned above, an additional angle droop control loop, referred to as adaptive power reference control (APRC), is proposed.The APRC is only active during voltage sags to avoid interfering with the steady-state P − f control.It can improve the system damping during voltage sags and adaptively adjust the power set-point of the VSG to keep the system stable even when no SEP exists.
The contributions of this work can be summarized as follows: • A TS study is conducted to determine the stability boundaries and stability margins of a VSG-GFLI system.This allows quantitatively analyzing the impacts of different factors such as dispatch level of the VSG and grid impedance on the TS of the paralleled system.
• An additional controller for the VSG, called APRC, is proposed to improve the damping of the angle dynamics when an SEP exists.Moreover, the APRC stabilizes the system even without the presence of an SEP by adaptively reducing the VSG dispatch level.The APRC is designed to keep the OP of the paralleled VSG-GFLI system away from the stability boundaries derived from the TS study mentioned above.The contributions of the TS study and the APRC are listed in Table I.
This paper is structured as follows.The model configuration and the TS study of the paralleled system are, respectively, detailed in Sections II and III.The APRC is proposed in Section IV.The experimental evaluations of the findings are provided in Section V. Finally, the conclusions are presented in Section VI.

II. SYSTEM CONFIGURATION
The studied system is described in Fig. 1.V FM and V FL are the voltages at the point of connection of the VSG and GFLI, respectively.The voltage angle of the VSG is denoted as δ while the output angle of the PLL in the GFLI is θ.V 1 is the voltage magnitude at a common bus between the VSG and the GFLI.The grid, i.e., an infinite bus, is emulated by an ideal voltage source, whose output voltage and angle are V g and θ g , respectively.Z 1 and Z 3 represent the transmission lines connecting the VSG and the GFLI to the common bus, respectively, and Z g is the transmission line connecting the common bus to the grid.I g , I 1 , and I 3 are the currents injected by the grid, the VSG, and the GFLI, respectively.A phasor diagram of the paralleled system is shown in Fig. 2.
This section first introduces the control models of the VSG and the GFLI.As the common bus in Fig. 1 is the only coupling between these two IBRs, their interactions are reflected in the common bus voltage.Since the voltage angle reference is chosen at the common bus for computational convenience, as shown in Fig. 1, the interactions between the VSG and the GFLI can be studied by monitoring V 1 and θ g .As θ g can be expressed in terms of V 1 , as shown in Section II-B, the impacts of the IBRs on each other are reflected in the variations of V 1 .Hence, an expression of V 1 as a function of the voltage angles, i.e., δ and θ, expressed by can be used to investigate the stability of the paralleled system.The derivation of (1) is presented in Section II-B.It is worth noting that choosing the angle reference at the common bus does not eliminate the dynamics of the voltage angle at this bus.Instead, the angle dynamics at the common bus can be investigated by monitoring variations in θ g .
A. VSG and GFLI Model 1) VSG Model: The VSG is treated as a controlled voltage source.Its control diagram is summarized in Fig. 3(a).V FM,abc and I f,1 are the values of V FM and the VSG filter current in a natural reference frame (NARF), respectively.The voltage and current controllers are implemented by vector control [1], [28].The active power controller (APC), which mimics the swing equation of SGs, is governed by while the droop-based reactive power control (RPC) can be presented as In (2), ω 0 , ω VSG , and P 0 are the nominal frequency of the grid, the internal frequency, and the active power set-point of the VSG, respectively.J represents the inertia term of the VSG, while the droop setting of the governor and the damping term of the swing equation are combined in D p .δ VSG is the instantaneous angle of the VSG output voltage.For the RPC of (3), V 0 , V ref , and Q 0 denote the nominal voltage of the VSG, the voltage reference for the voltage control loop, and the reactive power set-point of the VSG, respectively.k q is the Q-V droop gain.The active and reactive power injected to the common bus by the VSG, respectively denoted as P VSG and Q VSG , are and ).As the bandwidths of the voltage and current loops are much higher than that of the primary control [28], it is reasonable to assume V ref and V FM are approximately equal.Therefore, substituting for Q VSG from ( 5) into (3), and choosing the angle of the common bus voltage as the reference gives Solving ( 6) for V FM gives where Thus, V FM can be explicitly expressed in terms of δ and V 1 .
In low short circuit ratio (SCR) areas, the current limitation of VSGs might not be triggered due to high grid impedance [24].As this paper aims to study the stability of the VSG-GFLI system in low-SCR areas, scenarios when the current limitation is inactive are studied in this work.Taking the current limitation into consideration will be a continuation of this work.
2) GFLI Model: Unlike the VSG, the GFLI operates as a controlled current source.Its control diagram is presented in Fig. 3(b).V FL,abc represents the values of V FL in a NARF.A PLL is employed to track and generate the grid frequency measurement, denoted as ω GFLI .I d and I q are the direct (d-) and quadrature (q-) components of I 3 , respectively.They are regulated by vector control.As the current control bandwidth is significantly higher than that of the synchronization loop governed by the PLL, the current control dynamics are negligible in the TS study of the GFLI [3].Hence, I d and I q are assumed to be equal to their reference values, i.e., I d,ref and I q,ref .In addition, only the PLL performance is considered in the TS study of the GFLI.A synchronous reference frame PLL (SRF-PLL) is used in this article to force the q-component of V FL , i.e., v FLq , to zero via a proportional-integral (PI) controller.Thus, the instantaneous voltage angle of the GFLI is obtained as where v FLq = I d X 3 + I q R 3 − V 1 sin(θ), and k pθ and k iθ are the proportional and the integral gains of the PI controller [11].As the angle reference is chosen at the common bus, the phasor of the GFLI output current is , and θ v1 is the instantaneous angle of the common bus voltage.

B. Derivation of the Common Bus Voltage
As mentioned in the introduction of Section II, the interactions of the two IBRs can be studied via the dynamics of V 1 .This section aims to derive an expression for V 1 with respect to δ and θ.
From Fig. 1, with Letting Since the angle of the common bus voltage is chosen as the reference, as shown in Fig. 1, ( 12) can be decomposed as Rearranging ( 13) and ( 14) leads to Since θ g and V FM are not variables of (1), their expressions in terms of V 1 , δ, and θ should be derived.If sin(δ + θ 1g ) is different from zero, dividing ( 15) by (16) gives As V FM is eliminated in (17), an expression of θ g can be obtained by rearranging (17).Eq. ( 17) is equivalent to where M = V g Y g1 , N = |I 3 | Z eq , and β = ϕ+θ eq .Letting , θ g can be solved as In this study, V 1 cannot be expressed explicitly as a function of δ and θ.Instead, an equation consisting of only V 1 , δ, and θ is aimed to be obtained.Eq. ( 13) is a candidate.Nevertheless, apart from V 1 , δ and θ, in (13), there are two more variables which are V FM and θ g .It is worth mentioning that V g and the grid impedance (or admittance) are assumed to be constants in (13).However, V FM and θ g can be expressed in terms of V 1 , δ, and θ as shown in (7) and (20) or (21).Substituting (7), (20), and ( 21) into (13) for V FM and θ g gives an equation consisting of only V 1 , δ, and θ.Solving this equation for V 1 with δ and θ as parameters gives a root that is in the form shown in (1).However, due to the complexity of equation ( 13), it is difficult to derive an explicit root of V 1 as in (1).Alternatively, eq. ( 13) can be solved numerically for V 1 .By solving this equation for V 1 with a given pair of (δ, θ), a value of V 1 at the corresponding (δ, θ) can be obtained.
An example of how V 1 changes with variations in δ and θ is shown in Fig. 4(a).In this work, the VSG is installed to support a GFLI in a remote area of the network.Hence, the VSG should be located closer to the GFLI compared to the infinite bus.As the common bus is in the local area of the two IBRs and this area is in a remote part of the network, the distances from the common bus to the VSG and the GFLI are shorter than that to the infinite bus.Thus, Z 1 and Z 3 are much smaller than Z g .Therefore, the angle between the common bus and the VSG, i.e., δ, is much lower compared to the angle between the common bus and the infinite bus, i.e., −θ g , since the active power has a strong relation with the angle.Hence, δ and θ are not expected to grow to a high value above 90 • in this study.
As shown in Fig. 4(a), there is an upper limit in δ for each value of θ.With a δ value higher than the limit, no real value of V 1 exists.This limit is where the transition between the top and the bottom surfaces of V 1 occurs.These two surfaces are corresponding to the two solutions of θ g as presented in (20) and (21).As shown in Fig. 4(a), a large region of the top surface is determined by (20) while the remaining area of the top surface and the whole bottom surface are obtained by (21).It implies that as the angle difference between the VSG and the infinite bus, i.e., δ − θ g , grows, the common bus voltage reduces.In Fig. 4(b), for a given θ value, e.g., θ = 20 o , V 1 reduces as (δ − θ g ) or −θ g increases.In addition, these angles are above 90 o when the OP is on the bottom surface.In Fig. 4(a), as θ increases, the limit of δ first reduces and then rises when θ approaches 90 • .A higher limit of δ does not necessarily mean a larger stability margin, as presented below in Section III.Besides, on the top surface of the V 1 plot, as δ increases, V 1 reduces until the OP reaches the limit.The OP then transits to the bottom surface, and V 1 decreases with reductions in δ.Unlike δ, a growth of θ always results in a drop of V 1 .

III. TRANSIENT STABILITY ANALYSIS
A brief summary of the equal-area criterion (EAC) for a single IBR, i.e., VSG or GFLI, is first given in this section.Then, a stability boundary is derived for the VSG-GFLI system, which enables quantitatively analyzing the impacts of different parameters on the stability margin of the paralleled system.
This study investigates the angle synchronization of the IBRs and the grid after faults.The synchronization is mainly governed by the APC in a VSG [18] while it is implemented via a PLL in a GFLI [3].In addition, the time scales of the inner voltage and current loops are much faster than that of the APC and the PLL [3], [18].Hence, the APC and the PLL are focused in this study.

A. Impact of the Grid Voltage on TS of a Single IBR
This section provides a brief summary of the EAC-based TS analysis for a single IBR, i.e., VSG or GFLI, with a consideration of variable grid voltage, i.e., V g .Two separate systems, each containing only a VSG or a GFLI, are described in Fig. 5.An IBR becomes unstable if its angle, i.e., δ or θ, exceeds the post-fault unstable equilibrium point (UEP) angle, i.e., δ u for the VSG and θ u for the GFLI [18].The angle increase after fault clearance is caused by the inertial response of the VSG and low damping in the synchronizing loops [11], [15].It is worth noting that, in theory, the OP of an IBR might converge to another SEP in the next cycle of the power-angle curve of a VSG (or the voltage-angle curve of a GFLI) after the post-fault UEP is exceeded [14].However, due to the extremely severe transients that the IBR and the system experience (given the transients violate the permissible operation limits of the IBR), protections will be activated to isolate the IBR.This isolation is also considered as unstable operation of the IBRs.Thus, in this study, passing the UEP is used as the stability criterion of the IBRs, similar to the studies in [18], [29].
Fig. 5 describes how V g affects δ u and θ u , and hence, the TS of a single VSG or GFLI.A reduction in the grid voltage level results in lower δ u and θ u , leading to smaller stability margins for the IBRs.Thus, in general, if the voltages at nearby bus bars of the VSG or the GFLI do not recover quickly after the fault clearance, the VSGs and GFLIs are prone to transient instability.

B. Transient Stability Boundary of VSG-GFLI Systems
After fault clearance, (δ − θ g ) is usually at a high value due to the virtual acceleration of ω VSG during the fault.As shown in Fig. 4b and discussed in Section II-B, high values of (δ − θ g ) can lead to severe drops in V 1 .These voltage drops at the common bus negatively impact the TS of the VSG-GFLI system.
With the conventional EAC method, two separate studies must be conducted to investigate the TS of the angle of each IBR.Hence, the impacts of one IBR on the TS of the other are difficult to be revealed.In this section, a study that considers both the IBR angles in determining the system stability boundary is proposed.
As mentioned in Section II-B, a growth in (δ − θ g ) causes reductions in V 1 .Besides, as discussed in Section III-A, voltage drops at a nearby bus bar accelerate the movement of the OP of an IBR toward the unstable region.By investigating V 1 and taking the power and current injection references of the VSG and GFLI into consideration, the stability boundaries of the paralleled system can be determined.
1) Stability Boundary for VSG: During a fault, δ − θ g is likely to grow to a high value.For the VSG to be stable, after fault clearance, its frequency must always decelerate, i.e., until its OP crosses an SEP for the first time.From the APC shown in Fig. 3(a) and ( 2), the condition in ( 22) is satisfied if Since δ is typically lower than 90 • as mentioned in Section II-B, substituting for P VSG from ( 4) into ( 23) and rearranging give As the system is more prone to instability in dominantly inductive grids [24], and the IBR is not supposed to absorb active power, i.e., δ < 0, during faults, only ( 24) is considered in this work, due to the space limitations.
An example of V c,VSG with P 0 = 25 MW is displayed together with the V 1 plot in Fig. 6(a).The surface V c,VSG divides the top surface of V 1 into area A, where V c,VSG is higher than V 1 , and area B, where V c,VSG is lower than V 1 .Areas C and D are separated by the intersection of V c,VSG and the bottom surface of V 1 .Areas A and D are the acceleration regions, i.e., d ωVSG dt > 0, while areas B and C are where ω VSG decelerates, i.e., d ωVSG dt < 0. As (δ − θ g ) < 90 • , when the OP is on the top surface, the intersection between V c,VSG and the top surface of V 1 , i.e., line I, is the set of SEPs.In contrast, as (δ − θ g ) > 90 • , when the OP is on the bottom surface, the intersection of V c,VSG and the bottom surface of V 1 , i.e., line II, indicates the set of UEPs.Besides, line III is where the transition between the top and bottom surfaces of V 1 is located.An analogy between the above discussion and the P − δ plot can be realized by comparing Fig. 5(a) and Fig. 6(a).
(ω VSG − ω 0 ) grows to a positive value at the fault clearance due to the acceleration of the frequency during a fault.It is known that As  decelerates.This attempts to slow down the growth of (δ−θ g ).If (ω VSG − ω 0 ) reaches zero and turns negative before hitting Line II, (δ − θ g ) reduces, leading to a movement of the OP toward Line I and the SEP.Otherwise, once the OP enters region D, as V c,VSG > V 1 , hence d ωVSG dt > 0, and (δ − θ g ) grows.Therefore, the OP moves away from Line I and Line II, following the increasing direction of (δ − θ g ).The system then becomes unstable.
After a fault, the OP is likely to enter the deceleration areas B and C. If the OP always stays in areas B and C, and then comes back to area A, the VSG can stably recover despite some angle swings.Nevertheless, if the OP crosses line II and drifts into area D, ω VSG accelerates again, and ω VSG starts deviating from ω 0 .In such a case, the system becomes unstable.Thus, line II in Fig. 6(a) is a stability boundary for the VSG angle, δ.
2) Stability Boundary for GFLI: From (9), the closed-loop diagram of the PLL can be obtained as in [11].Similarities between the synchronization loop of a PLL [11] and APC of the VSG can be realized.The terms I d X 3 + I q R 3 and V 1 sin(θ) the GFLI are analogous to P 0 and P VSG of the VSG, respectively.Hence, the TS of the GFLI can be analyzed similarly to that of the VSG.When the OP is within the bottom surface of V 1 , must be satisfied such that the frequency generated by the PLL, i.e., ω GFLI , always decreases until the OP reaches the SEP for the first time after the fault clearance.The condition in ( 27) is held if while the OP is on the bottom surface of V 1 , the GFLI will be unstable.An example plot of V c,GFLI is shown in Fig. 6(b).The intersection of V c,GFLI and the bottom surface of V 1 , i.e., line indicates the stability boundary for θ.If the OP crosses this line, making V 1 lower than V c,GFLI , the GFLI becomes unstable.By applying the conditions in ( 24) and ( 28) on ( 13), a stable region of δ and θ can be identified.The intersection between the bottom surface of V 1 and V c,VSG defines the stability boundary of δ, and the intersection between the bottom surface of 1 c,GFLI defines the stability boundary of θ.An example of the stability boundary of δ and θ can be found in Fig. 6(c).If the angle trajectory travels to the region where the bottom surface of V 1 is lower than V c,VSG or V c,GFLI , it will diverge from the SEP, and the system is unstable for at least one swing.Besides, the intersection of V c,VSG , V c,GFLI , and the top surface of V 1 is the SEP.A 2-dimensional (2-D) plot of the stability boundaries is available in Fig. 6(d).
As mentioned in Section II-B and Fig. 4(b), the bottom surface of V 1 is where (−θ g ), hence (δ − θ g ) and (θ − θ g ), are greater than 90 o , and where the OP is, after the clearance of a severe fault.The internal frequency of the VSG and the GFLI are greater than ω 0 due to the acceleration of ω VSG and

C. Validation of Transient Stability Boundaries
Several simulation tests are conducted to verify the correctness of the stability boundaries derived above.The tested system, whose parameters are listed in Table II, consists of a VSG and a GFLI connected to an ideal grid via the grid impedance as shown in Fig. 1.A fault is applied at t = 30 s by lowering V g to 0.6 pu.The fault duration is set to 1.105 s, 1.123 s, and 1.1235 s to create a stable, a marginally stable, and an unstable case, respectively.The results of these cases are presented in Figs.7-9, respectively.
The set of results shown in Fig. 7 are generated with the shortest fault duration.The angle trajectory starts at point 1 right after the fault clearance.It then drifts to points 2 and 3 until reaching point 4. At point 4, the trajectory turns around and starts moving back to the top surface of V 1 and the SEP via points 5, 6, and 7.As the trajectory does not cross the stability boundaries, a stable recovery of the system is observed in the time-domain plots of Fig. 7.The voltage, power, frequency, and angles converge to the pre-fault conditions, despite some post-fault swings.Similarly, the results of a marginally stable case are presented in Fig. 8.In this case, the turnaround point of the trajectory is right on the determined stability boundaries.Hence, it takes the system longer to recover to its SEP.Finally, an unstable case is investigated in Fig. 9.The angle trajectory crosses the stability boundary of the VSG first and then that of the GFLI.In the time-domain plots of Fig. 9, the frequencies diverge from their nominal value, leading to a synchronization failure.Moreover, at the instant the frequencies start re-accelerating, δ and θ are about 13.7 • and 17.2 • , respectively, as highlighted in Fig. 9(f).These values match the position of point 4, where the trajectory crosses the VSG boundary, in Fig. 9(e).
In Figs.7-9, the angle trajectories closely align with the V 1 surface.This validates the correctness of ( 13), ( 7), (20), and (21).Moreover, the angles recover after the fault clearance if their trajectory stays within the stability boundaries.However, if the trajectory travels beyond the boundaries, the angles diverge from the SEP, and the frequency re-accelerates.In addition, the coordinate where the angle trajectory crosses the VSG boundary matches the angle values when the frequency re-accelerates in the time-domain plots.These validate the correctness of the determined boundary.Besides, the location of the SEPs in Figs.The method presented above is meant for determining the stability boundary of the IBR angles (the set of UEPs) and the stability margin of the system.Besides, the control parameters, such as PI parameters of the PLL, impact the angle trajectory evolution.Under a given voltage sag condition, these parameters can affect the chance that the angle trajectory crosses the identified boundary.Once a desirable angle region is derived, the required PI parameters can be back-calculated from the stability boundary.Studying the dynamics of the angle trajectory can be a future work of this analysis.A few tools that can possibly be employed for studying if the angle trajectory crosses the identified boundary or not are phase portrait analysis [15] and backward integral [30], [31].
An improvement in the damping of the IBR control [11], [15] can prevent the angle trajectory from evolving to the unstable region determined above.However, the effects of the control parameters on the system damping are not within the scope of the above analysis.Besides, if the GFLI is electrically close to the VSG, ω GFLI is heavily dependent on ω VSG .To validate the stability boundary of the GFLI separately, Z 1 must be increased to move the VSG away from the GFLI.However, as this paper aims to study the VSGs that are installed to support GFLIs in weak grids, that scenario is out of the scope of this paper.Moreover, the above analysis focuses on a single-VSG-single-GFLI system.The TS study of wider networks with multiple VSGs and GFLIs is a continuation of this work.

D. Impacts of Various Parameters on the Transient Stability of the VSG-GFLI System
The stability margin can be evaluated via the stable region on the bottom surface of V 1 as shown in Fig. 6(d).This area is where ω VSG decelerates after a fault as (δ − θ g ) is high in the fault recovery.Hence, like the EAC, the size of the deceleration region can be used to evaluate the stability margin of the system.In this study, the is not only dependent on the area of stable region but also on the difference between the bottom surface of 1 and V c,VSG .A great difference between V 1 and V c,VSG in this area implies a large value of (P VSG − P 0 ), hence a high deceleration force.Thus, a volume presentation, referred to as deceleration volume (DV), as shown in Fig. 10, is used as a stability measurement in this analysis, instead of an area as per the EAC.This volume is the space between the stable area depicted in Fig. 6(d) and the portion of the V c,VSG surface that is located right under the stable region.The DV can be calculated as where SR is the stable region derived in Figs.6(d) and 10(b), restrained by Line II, Line III, Line b, and θ = 90 o .The limit of θ is set to 90 o in this calculation because the common bus is assumed to be in a local area of the GFLI.It is worth noting that the V 1 surface used for calculating the DV is normalized in a per-unit scale.
The contribution of the DV to the stability can be seen as below.From the EAC, it is known that the maximum available deceleration area (DA) is calculated as where δ s and δ u are the SEP and UEP angles of the VSG, respectively.The larger the DA is, the higher the stability margin of the system is.For a lossless transmission line, as P 0 = 1.5 Vc,VSGVFM sin(δ) X1 and P VSG = 1.5 V1VFM sin(δ)

X1
, hence, As shown in Section III-B, the stable region is a deceleration region.For a given θ value in the stable region, over a range of δ, e.g., between Line II and Line III, a higher DV indicates a larger V 1 − V c,VSG , as DV is calculated per (29).Thus, per (31), a larger V 1 − V c,VSG results in a larger DA for the VSG.Thus, the frequency has more room to decelerate after a fault clearance with a higher DV.In this section, the impacts of the grid impedance, the distance between the VSG and the GFLI, and the dispatch level of the VSG on the stability margin of the paralleled system are investigated.Each of the above parameters is varied from that of the base case listed in Table II to create different test cases.The DV of the system in each case is calculated and compared with that of other cases to reveal the effects of those parameters on the TS of the system.
1) System Strength: In this test, the grid impedance, i.e., Z g , is varied to investigate its impacts on the DV of the system.As shown in Table III, as Z g increases, the DV reduces.Hence, the OP is more likely to cross the stability boundaries after large-signal disturbances when it comes to weak-grid conditions.This implies that the system is more prone to instability when the grid strength, measured by the SCR [32], reduces.
2) Distance between VSG and GFLI: The distance between the VSG and the GFLI is adjusted by changing Z 1 .As shown in Table III, a growth in Z 1 results in a reduction in the DV.If the VSG is distant from the GFLI, the voltage support provided by the VSG to the GFLI is limited.Hence, the voltage at the common bus tends to drop lower when the VSG is remote from the GFLI.Thus, as shown in Fig. 5, deeper drops in V 1 deteriorate the system TS.
Another case when the paralleled system is close to the infinite bus is also investigated.In this case, Z g is only 0.13 pu, and the GFLI is well supported by the VSG as Z 1 is TABLE IV: The scope of the TS study in this paper compared to existing studies.
3) Power Dispatch Level of VSG: In addition, the power dispatch level of the VSG can affect the system stability significantly.Three different values of P 0 are examined in this test.A higher P 0 results in a smaller DV as summarized in Table III.When the dispatch level of the VSG increases, its stability boundary, i.e., line II, is pushed toward line III, resulting in a reduction in the area of the stable region.Thus, the VSG and the whole system are closer to the instability.Therefore, reducing P 0 during voltage sags is preferable to enhance the stability margin of the system.This is the motivation of the proposal detailed in Section IV.
4) Power factor angle of GFLI: Apart from the dispatch level of the VSG, the proportion of reactive current, i.e., I q , in the total current injected by the GFLI also affects the TS margin via impacting the output voltage level of the GFLI.This proportion can be investigated via the power factor angle of the GFLI output current, i.e., ϕ = tan −1 Iq I d .The DVs of three cases with different ϕ values are listed in Table III.A more negative ϕ results in a higher proportion of reactive power from the GFLI.Hence, the network voltage receives more support from the GFLI with more negative ϕ.As a result, the TS margin of the case with the most negative ϕ value is the highest.Therefore, a more reactive current injection from the GFLI is more beneficial for the stability of the paralleled system as well as the VSG.
Table IV summarizes the differences between the scopes of this study and those of other existing works.

IV. ENHANCED CONTROL FOR VSGS TO IMPROVE TRANSIENT STABILITY OF THE SYSTEM
In this section, an additional control loop for VSGs, referred to as the APRC, is introduced to improve the TS of the paralleled system.As discussed in Section III-D3, a high active power set-point of the VSG can negatively impact the stability of a VSG-GFLI system.Thus, during voltage sags, the APRC adaptively modifies the power set-point of the VSG such that the OP can stably converge to an SEP.The APRC can improve the system damping by effectively reducing the P − f droop gain to allow the OP to settle to an existing SEP.Moreover, if an SEP is absent, the power set-point of the VSG is adaptively adjusted by the APRC to create a new SEP.

A. Adaptive Power Reference Control
Fig. 11 shows how the OP of the VSG evolves during a voltage sag.For a given V 1 value, δ 0 is the angle value at which, P VSG is equal to P 0 .Thus, δ 0 is the angle where δ try to converge to, for a given V 1 value.It is worth noting that during a transient, as V 1 varies, hence δ 0 also changes, and δ 0 is not just a steady-state value.The position where δ equals δ 0 is defined as an equilibrium point or an SEP if it is within the top surface of V 1 .After a large-signal disturbance, the OP of the VSG deviates from the SEP.As the OP then moves toward the post-disturbance SEP thanks to the swing equation, δ and δ 0 converge to each other as described in Fig. 11(a).Hence, the difference between δ and δ 0 , i.e., ∆δ = δ 0 − δ, converges to 0. However, the absence of an SEP makes ∆δ first reduce and then increase as the OP drifts to the bottom surface of V 1 as shown in Fig. 11(b).Eventually, δ and δ 0 diverge from each other, and the system becomes unstable.Because ∆δ is always positive without the presence of an SEP and reduces as the OP moves closer to V c,VSG , ∆δ can be used to adjust the active power reference of the VSG to bring back an SEP if none exists.Based on the above discussion, the APRC is added to the VSG control as presented in Fig. 12(a).This control loop requires V 1 , hence leading to the need of a communication link to transmit V 1 measurements to the VSG.With the measured V 1 , δ and δ 0 can be calculated as and where ϕ 1 is the angle of Z 1 .By linearizing cos(x ) as cos(x) ≈ π 2 − x, when x is around π 2 , the term This simplification allows eliminating the necessity of knowing ϕ 1 when implementing the APRC.However, Z 1 is still required.As the common bus is in the same local network of the VSG and the GFLI, the information of Z 1 is assumed to be available.Although the information of Z 1 is needed, the APRC is robust to unintended changes in Z 1 , as elaborated in Section IV-B below.
Without an SEP and the APRC, the power error, i.e., P 0 − P VSG , never diminishes to zero.Hence, ω VSG cannot converge to ω 0 and keeps growing due to the integrating action of the APC, causing an unstable response.Whereas, with the APRC active, P 0 is decreased by k ∆δ to form P ′ 0 .The APRC gives the APC one more degree of freedom to make the input of the integrator zero by adjusting P 0 .Hence, it allows the existence of a new SEP as depicted in Fig. 11(c).To avoid interfering with the P − f control in the normal operation, the APRC is only active when V 1 falls below a threshold value.The deactivation of the APRC occurs if V 1 recovers above the threshold value, and ∆δ remains at zero for a predefined interval.

B. Transient Stability Improvement and Gain Tuning
The tuning of gain k is presented in this section.Substituting (34) into the diagram in Fig. 12 and To avoid positive feedback in the APC, k should be set low enough such that 0 < A < 1 when V 1 and V FM are in their normal operating range, i.e., above 0.9 per unit (pu).To tolerate uncertainties in Z 1 , k should be chosen such that A is below 0.6 with V 1 and V FM in their normal range.During voltage sags, V 1 decreases, leading to an increase in A. From (37), with the APRC activated, the effective droop gain of the VSG reduces by A. As shown in [29], reducing the droop gain during voltage sags helps extend the critical clearing time of the VSG, thus improving the stability during and after the fault clearance.Moreover, from (37), the APRC makes the inertia and damping terms of the VSG reduce by where ζ approximates the damping ratio of the VSG APC [15], and 0 < C < 1, the overall damping of the VSG power angle is improved with the APRC online.Moreover, when no SEP exists, V 1 reduces to a value, i.e., V 1,min , where A and (1-A) become 1 and 0, respectively.When V 1 = V 1,min , the power error is set to zero before reaching the integrator in the swing equation.As the integrator tries to force its input to zero, it adjusts ω VSG and δ such that V 1 converges to V 1,min .Thus, a new stable steady-state is achieved.In other words, the APRC adjusts P ′ 0 to keep the steady-state of V 1 from falling below V 1,min .Hence, k is chosen such that when V 1 is at V 1,min , A equals 1.Hence, k should be set as V FM,min can be a few percent less than V 0 .Based on the analysis presented in Section III, V 1,min can be chosen to reserve a sufficient stability margin for the GFLI.By this approach, a properly tuned APRC can enhance the TS of both VSG and GFLI.
In addition, as the information of Z 1 is utilized in the APRC, the robustness of the APRC against uncertainties in Z 1 must be investigated.Assuming that an unpredictable line tripping makes Z 1 rise to Z ′ 1 = α Z 1 , where α > 1.The gain k is kept the same as the growth in Z 1 is not updated in the APRC.Multiplying both the numerator and the denominator of (39) by α leads to (40) Substituting for k from (40) into gain A results in As shown in (40), k ′ is the desirable gain value that keeps the steady-state value of V 1 above V 1,min when the impedance between the common bus and the VSG is Z ′ 1 .Since k equals k ′ α and is not updated in the APRC, the increase by α in Z 1 is reflected in gain A, as presented in (41).In fact, k is expected to reduce by α when Z 1 increases by α.As k and Z 1 are not updated when an unintended change in Z 1 happens, their deviations cancel the impacts of each other on gain A. Thus, when Z 1 rises due to line trippings, P ′ 0 drops to a lower value to keep V 1 from falling below V 1,min .This reaction of the APRC is reasonable because when the power transfer capability of the line reduces due to a line tripping, the power injection of the VSG decreases to keep the system stable.Hence, the operation of the APRC is robust to changes in Z 1 .
The discussion about the robustness of the APRC above is also applicable to cases where Z 1 decreases unexpectedly, i.e., α < 1.As the impacts of α on gain A in this discussion is always cancelled, it does not matter if α is greater or less than one.Since an increasing Z 1 is more practical and likely to occur after a fault clearance due to a line tripping to isolate the faulty network, only this case is focused.

C. Strengths and Shortcomings of the APRC 1) Advantages:
• The APRC can effectively enlarge the deceleration region of the VSG.• The APRC is designed to keep the common bus voltage above a certain minimum value.By setting this minimum value above or at least at the transition line of the two V 1 surfaces, the crossover between the OP and the stability boundaries can be avoided.Therefore, the OP of the whole paralleled VSG-GFLI system can stay on the top surface of V 1 , and the frequency always decelerates to an SEP after a transient.An impedance estimation can be used to update the gain k when Z 1 changes.

• Adaptive operations:
-With an SEP, it is proved that the APRC improves damping of the APC of the VSG, hence restraining an excessive growth in the power angles and suppressing severe power swings after fault.Besides, the APRC allows the power to converge to its pre-fault level even during transient events.-Without any SEP, the APRC reduces its power reference to create an intersection between the V 1 and V c,VSG , hence bringing back an SEP for the OP to converge to.

2) Shortcomings:
• The requirement of a measurement for V 1 .
• Currently, this proposal is applicable for one pair of VSG-GFLI.Extending the proposal to a system with multiple pairs might require more measurements and communication links.This extension can be a continuation of this study.Brief comparisons between the APRC proposed in this work and the existing studies are presented in Table V.

V. EXPERIMENTAL VALIDATION
In this section, the correctness of the stability boundaries discussed in Section III-B and the performance of the APRC are experimentally validated.The experimental setup diagram is depicted in Fig. 13.The VSG and the GFLI are built in an Imperix Power Rack.Their controllers are developed in an Imperix B-Box platform.The outputs of the converters are connected to a Regatron TC.ACS grid simulator via LC filters and grid impedance, which is emulated by three-phase inductors.V g is lowered to emulate a three-phase balanced fault in the tests below.The parameters of the experimental setup can be found in Table II.The short-circuit ratio at the common bus is about 1.6 in the tests below.

A. Stability Boundary of the VSG-GFLI System
Firstly, the correctness of the stability boundary of the VSG is validated.A fault with a residual voltage of 0.68 pu is applied at t = 4 s.The fault is cleared at t = 5.28 s or t = 5.3 s to make the system stable or unstable, respectively.The results of the stable case are presented in Fig. 14 As the trajectory does not cross the stability boundary, the system can stably recover to its SEP.The stable recovery can be observed in the time-domain plots depicted in Fig. 14(c) and 14(e).After a few swings, the frequency, the angle, the voltage, and the power measurements converge to their pre-fault values.Furthermore, the angle trajectory only travels within the V 1 surface.This verifies the accuracy of the common bus voltage derivation in Section II.
However, when the fault is cleared at t = 5.3 s, the angle trajectory drifts across line II, into the unstable region as shown in Fig. 14(b).Thus, in the time-domain plot presented in Fig. 14(d), the frequencies cannot return to their nominal values and re-accelerate after the fault clearance until the protection is triggered and disconnects the paralleled system from the grid.In Fig. 14(f), the voltages collapse shortly after the fault clearance.P VSG and δ fall to negative values before the protection is triggered, indicating a complete failure of the system.As shown in Fig. 14(d), the values of δ and θ at the instant when the ω VSG re-accelerates after the fault clearance, i.e., δ = 8.7 • and θ = 7.2 • , match the location where the trajectory crosses line II, i.e., point 4, in Fig. 14(b).This verifies the correctness of the discussion in Section III-B.Moreover, the pre-fault steady-state values of δ and θ, i.e., δ = 6.7 • and θ = 4.6 • , are similar to the location of the SEP identified in Fig. 14(a) and 14(b).

B. Effectiveness of the APRC
In addition, the effectiveness of the APRC is experimentally examined in this section.V FM,min and V 1,min are chosen as  0.98 pu and 0.73 pu, respectively.Hence, the gain k of the APRC is set to 4350.The threshold value of V 1 for activating the APRC is 0.89 pu.The sampling time of V 1 is 0.1 s to emulate a communication delay.A case with an SEP and a case without any SEP are examined below, followed by a test on the robustness of the APRC against Z 1 variations.
1) Voltage Sag with an SEP: In this case, a grid voltage sag with a residual voltage of 0.81 pu is applied at t = 4 s and remains in the system.In Fig. 15, the results of the case with an SEP existing during the voltage sag are presented.Fig. 15(a) and 15(b) show a set of results when the APRC is inactive.Without the APRC, ω VSG and ω GFLI cannot converge to their nominal value.They re-accelerate and keep growing until the protection is triggered, as shown in Fig. 15(b).Besides, V FL and V 1 in this case, as shown in Fig. 15(a), drop severely.The fall of V 1 causes a reduction in the maximum transferable power of the VSG.Thus, although P VSG can reach P ′ 0 after the disturbance, it then collapses as V 1 is too low for P VSG to recover.Hence, a complete failure of the system can be observed in Fig. 15 However, as shown in Fig. 15(c) and 15(d), with the APRC enabled, the system remains stable after the fault occurs.In Fig. 15(c), P ′ 0 is lowered when V 1 falls below the threshold value.This reduces the amount of power error fed to the swing equation, hence restraining the growth of ω VSG and δ.Eventually, ω VSG and ω GFLI converge to their nominal value.Additionally, δ, θ, V 1 , and V FL settle to a new stable steadystate, instead of becoming unstable.Due to the presence of an SEP, P ′ 0 and P VSG can return to the pre-fault active power set-point.The results in Fig. 15 validate the effectiveness of the APRC in enhancing the damping of the APC of the VSG.2) Voltage Sag without an SEP: In this test, the APRC effectiveness is validated when no SEP exists during a voltage sag.The grid voltage is set to 0.68 pu during the voltage sag, starting from t = 4 s, to eliminate the existence of the SEP.A set of results without the APRC is shown in Fig. 16(a) and 16(b).As shown in Fig. 16(a), P VSG cannot reach P ′ 0 and collapses eventually due to the absence of an SEP.This leads to a significant acceleration of ω VSG and a large frequency rise as shown in Fig. 16(b).Hence, the angles become unstable, and the voltages keep falling until the protection is triggered as presented in Fig. 16(a) and 16(b).Nevertheless, with the APRC active, a steady-state offset is observed in P ′ 0 and P VSG during the voltage sag, compared to their pre-fault values, as depicted in Fig. 16(c).The offset restores the existence of an SEP in Section IV-A.As a result, frequencies converge to their nominal angles, shown in Fig. 16(d), and the voltages, shown in Fig. 16(c), stably to new levels.It is worth noting that V 1 settles to the chosen V 1,min , which is 0.73 pu.Therefore, the APRC successfully prevents the steady-state of V 1 from falling below V 1,min by adjusting the VSG power set-point.Hence, a new SEP is created by the APRC, while it is absent when the APRC is inactive.
3) Robustness of the APRC against Z 1 Variations: Fig. 16(e) and 16(f) validate the robustness of the against uncertainties in Z 1 .A fault with a residual voltage of 0.68 pu occurs at t = 4 s.Z 1 is then changed from 0.27 pu to 0.53 pu at t = 11.9 s.The gain k is set to 3950 to achieve a V 1,min of 0.73 pu with an expected Z 1 of 0.27 pu.After the voltage sag occurrence, P ′ 0 tries to converge to 0.3 pu, and V 1 tends to settle to 0.73 pu, as shown in Fig. 16(e).Subsequently, in responding to the change in Z 1 , the APRC further reduces P ′ 0 to 0.23 pu to tackle the drop in V 1 .Eventually, V 1 converges to the chosen V 1,min value, i.e., 0.73 pu, as expected.The voltages, frequencies, and angles settle to a new stable steady-state as depicted in Fig. 16(e) and 16(f).Therefore, the increase in Z 1 does not affect the performance of the APRC in keeping the steady-state value of V 1 from falling below V 1,min .VI. CONCLUSIONS Installations of VSGs in remote GFLI-dominant areas improve the voltage and the frequency stability of these regions.However, an excessive power angle evolution of the VSGs during and after faults leads to voltage drops in these areas, hence causing adverse impacts on the TS of nearby GFLIs.Thus, the TS of a paralleled VSG-GFLI system is studied in this paper.Firstly, the stability boundaries and the stability margins of the angles of the two IBRs are determined based on analyzing the voltage at a common bus between the IBRs.The determined stability margin is represented in a volume presentation that allows quantitatively evaluating the TS of a VSG-GFLI system.Finally, based on the above analysis, an additional angle droop control loop, referred to as the APRC, is proposed to enhance the angle damping during voltage sags.Moreover, when no SEP exists during a voltage sag, the APRC can restore the existence of an SEP by adaptively reducing the power set-point of the VSG to keep the system stable.The effectiveness of the APRC has been analytically and experimentally validated.

Fig. 1 :
Fig.1:The studied system diagram.The VSG operates as a voltage source while the GFLI is treated as a current source.

Fig. 4 :
Fig. 4: (a) An example of how V 1 varies with changes in δ and θ.(b) An example of how V 1 varies with changes in −θg or δ − θg , given θ = 20 o .

Fig. 6 :
Fig. 6: An example of how the stability boundaries are determined: (a) Stability boundary of the VSG, (b) Stability boundary of the GFLI, (c) Stability boundaries of the VSG-GFLI system, and (d) 2-D top view of the stability boundaries.

Fig. 6 (
a), d ωVSG dt > 0 in A. Thus, ω VSG increases, and (δ − θ g ) tries to increase.The movement direction of the OP when (δ − θ g ) increases is shown in Figs.4(a) and 6(a).An increasing (δ − θ g ) in region A results in a movement of the OP toward Line I. In regions B and C, as V c,VSG < V 1 , hence d ωVSG dt < 0. Thus, ω VSG

Fig. 7 :
Fig. 7: Simulated responses of the system to a voltage sag when the system remains stable: (a) 3-D view of the angle trajectory, (b) Time-domain voltage and active power, (c) 2-D top view of the angle trajectory, (d) Time-domain frequency, (e) Magnified 2-D top view of the angle trajectory, and (f) Timedomain angles.

Fig. 8 :
Fig. 8: Simulated responses of the system to a voltage sag when the system is marginally stable: (a) 3-D view of the angle trajectory, (b) Time-domain voltage and active power, (c) 2-D top view of the angle trajectory, (d) Timedomain frequency, (e) Magnified 2-D top view of the angle trajectory, and (f) Time-domain angles.

Fig.
Fig. Simulated responses of the system to a voltage sag when the system becomes unstable: (a) 3-D view of the angle trajectory, (b) Time-domain voltage and active power, (c) 2-D top view of the angle trajectory, (d) Timedomain frequency, (e) Magnified 2-D top view of the angle trajectory, and (f) Time-domain angles.ω GFLI during the fault.If the operating point always remains in the decelerating region, i.e., d ωVSG dt < 0 and d ωGFLI dt < 0, on the bottom surface, the frequencies are then always able to decelerate and come back to an SEP.The stable region shown in Fig. 6 is such a region.The steps deriving the stable region above prove that d ωVSG dt < 0 and d ωGFLI dt < 0 are satisfied when the operation point stays in the stable region.

Fig. 11 :
Fig. 11: Side views of a common bus voltage analysis when a voltage sag occurs: (a) with an SEP, (b) without any SEP, and (c) with the APRC active during a voltage sag without an SEP.
(a) results in the equivalent diagram as shown in Fig. 12(b).Hence, the transfer functions of the P − f control of a VSG without and with the APRC are K noAPRC (s
(a), 14(c), and 14(e), while those of the unstable case are shown in Fig. 14(b), 14(d), and 14(f).In Fig. 14(a), starting from the fault clearance, indicated by point 1, the angle trajectory moves toward the stability boundary of the VSG, indicated by line II.It then turns around at point 4 and travels to the top surface of V 1 and the SEP via points 5, 6, and 7.

Fig. 14 :
Fig. 14: Experimental validation of the stability boundaries of the paralleled system.Stable case: (a) angle trajectory, (c) frequency and angle, (e) voltage and power measurements.Unstable case: (b) angle trajectory, (d) frequency and angle, (f) voltage and power measurements.

Fig. 15 :
Fig. 15: Experimental validation of the APRC with an SEP existing during a voltage sag.Without the APRC: (a) voltage and power, (b) frequency and angle measurements.With the APRC: (c) voltage and power, (d) frequency and angle measurements.

Fig. 16 :
Fig. 16: Experimental validation of the APRC without any SEP existing during a voltage sag.Without the APRC: (a) voltage and power, (b) frequency and angle measurements.With the APRC: (c) voltage and power, (d) frequency and angle measurements.With the APRC and a change from 0.27 pu to 0.53 pu in Z 1 : (e) voltage and power, (f) frequency and angle measurements.
Transient Stability of Paralleled Virtual Synchronous Generator and Grid-following Inverter Si Phu Me, Student Member, IEEE, Mohammad Hasan Ravanji, Member, IEEE, Milad Zarif Mansour, Student Member, IEEE, Sasan Zabihi, Senior Member, IEEE, and Behrooz Bahrani, Senior Member, IEEE Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
© 2023 IEEE.Personal use of this material is permitted.

TABLE I :
Contributions of the TS study and the APRC in this paper.

TABLE II :
Simulation and Experimental parameters.

TABLE III :
Deceleration volumes in various scenarios.

TABLE V :
Features of the APRC compared to existing methods.