Transient Stability Analysis of Virtual Synchronous Generator Equipped With Quadrature-Prioritized Current Limiter

A current limiter (CL), which protects virtual synchronous generators (VSGs) from overcurrents, may significantly alter the operation of the VSGs when activated. In this letter, a transient stability analysis of VSGs equipped with quadrature (q-)prioritized CL is performed. This study shows that in addition to the instability caused by the positive feedback of the primary controller, a VSG could become unstable after large disturbances due to the failure of the inner voltage controller. In this study, a stability criterion is provided for the voltage control loop.


I. INTRODUCTION
V IRTUAL synchronous generators (VSGs) require a current limiter (CL) in their control system to protect their switches from overcurrent during transients. However, a CL alters the voltage-controlled (VC) mode of a VSG to a currentsource-like behavior. Thus, the traditional power-angle (P − δ) curve of a synchronous generator is no longer applicable [1]. Hence, for current-limited VSGs, it is necessary to study the transient stability (TS) and the possibility of losing synchronization with the grid upon large disturbances.
Several studies on the TS of VSGs equipped with various types of CL are conducted in [2] and [3]. However, setting priority to the active or reactive current during faults is not offered by these methods, while this feature is required by grid codes. Injecting reactive current is preferred during faults to support the voltage. Hence, setting priority to reactive current is recommended by IEEE P2800 [4]. In this letter, the VSG voltage is aligned with the direct (d)-axis by regulating its quadrature (q-)component to zero. Hence, the q-current is equivalent to the reactive current of the VSG as long as the q-component of the voltage is zero. The q-component of the voltage may not be regulated to zero if the output of the q-voltage controller, which is the q-current, saturates. Giving priority to the q-current maximizes the limits of the q-current. Hence, it helps to prevent the q-current from saturating and keep the q-voltage around zero, thus aligning the reactive current to the q-axis. It is shown in Section III-A that the reactive current always aligns with the q-axis, even when the power angle is in a transient state, if the q-prioritized CL (q-CL) in Section II is employed. In this case, prioritizing q-current means setting the priority to reactive current. Moreover, injecting q-current extends the TS margin of a VSG [1]. Due to the benefits of prioritizing the q-current, as mentioned previously, equipping VSGs with a q-CL should be considered and studied.
However, the TS of q-prioritized-current-limited VSGs (q-CL-VSGs) is not studied thoroughly. In [5], d-prioritized CLs (d-CLs) are investigated. During faults, d-CLs push the d-current to the current limit, leaving the q-current at zero. This results in a constant value, i.e., 0 o , for the angle difference between the total output current and the d-axis of the VSG. Thus, the analysis of d-CLs can be significantly simplified by setting this angle difference to 0 o and eliminating variations of this angle difference. Similarly, this angle difference can also be set to a predefined negative constant by a mode-switching mechanism to increase the q-current injection of the VSG [1], [6]. Nevertheless, this simplification of the current angle does not apply to analyzing q-CLs, as the amount of q-current generated by q-CLs is not always pushed to the current limit, but depends on the grid and fault conditions as well as the dynamics of the primary control. Hence, in this case, the current angle against the d-axis of the VSG varies during and subsequent to faults. This makes the analysis of q-CLs more challenging despite their advantages. Although a power-angle (P − δ) curve of a q-CL-VSG is introduced in [7], the effects of grid impedance on its TS are not considered. In addition, the voltage controller in [7] is virtual-admittance-based, while the commonly used vector voltage control structure is not studied. It is shown in this letter that the voltage control does have impacts on the TS of VSGs. Hence, the TS study for q-CL-VSGs equipped with vector voltage control must be revisited.
To fill this gap, in this letter, a TS analysis for the q-CL-VSG is developed. The vector voltage control, which is commonly employed, is considered in this letter. It is found that the use of a q-CL together with the vector voltage control can affect the TS of VSGs, and the impacts of the voltage control should not be overlooked completely in the TS study. The main contributions of this study are as follows.
1) A novel power angle limit, caused by the disappearance of a stable equilibrium point (SEP) of the inner q-voltage controller (V q C), is determined for the VSG. Based on that, a TS criterion is developed for the V q C. 2) A P −δ curve for the q-CL-VSG is developed.

II. SYSTEM CONFIGURATIONS
The system studied is shown in Fig. 1. It consists of a VSG connected to an infinite bus, whose voltage is V g ∠θ g , via a transmission line, represented by X g , and an inductance-capacitance filter. The voltage at the point of connection of the VSG is V FM ∠θ FM .
The control system of the VSG consists of a primary controller, a voltage controller, and a current controller. The primary control includes an active power controller (APC), which is governed by the swing equation shown in Fig. 1, and a reactive power controller. P 0 and P VSG are a constant reference and the measured power of the VSG, respectively. θ VSG is the angle used for the Park transformations. ω VSG is the internal frequency of the VSG, which is equal to the nominal frequency, i.e., ω 0 , in a steady state. The voltage loop (VL) consists of two proportional-integral (PI) controllers, i.e., a d-voltage controller (V d C) and a q-voltage controller (V q C), which generate the references for the current controllers. When a severe fault occurs, the output current is limited to a maximum value, i.e., I max , by a q-CL to protect the VSG. The outputs of the q-CL are i * sd,sat and i * sq,sat . The q-CL is governed by two saturators shown in Fig. 1 [8], where As long as −I max < i sq,ref < I max , the output of the saturator, i.e., i * sq,sat , is equal to i sq,ref . After i * sq,sat is determined, if there is still available room within the current limits, the remaining room of current is allocated to the d-current by setting I d,max = −I d,min = I 2 max − i * 2 sq,sat ; otherwise, if |i sq,ref | reaches I max , i * sq,sat saturates to I max or −I max . Thus, I d,max and I d,min are pushed to zero. Hence, the magnitude of i s,d decreases to zero. When the d-or q-current, i.e., i s,d or i s,q , saturates, only the integrator of the saturated PI controller is disabled to avoid windup. The integrator output in the disabled PI controller is kept unchanged while its input is set to zero.

III. TS ANALYSIS
In this section, a discussion on a TS issue of the q-voltage loop (q-VL) is given. A P − δ curve of a q-CL-VSG is then introduced to analyze the instability caused by the APC.

A. TS Issue of the q-Voltage Control Loop
In this section, due to the high bandwidth of the current loop, i s,dq ≈ i * sdq,sat [1]. The diagram of the V q C is shown in Fig. 2

(a). As the q-current flowing through
As T c is much shorter than that of the VL, the dotted part in Fig. 2(a) resembles an integrator of the output of the controller, i.e., u v,q , with a gain of 1 T c . Letting δ = θ VSG − θ g , as given in [9] Authorized licensed use limited to the terms of the applicable license agreement with IEEE. Restrictions apply.
where M (i s,q ) = (I max X g ) 2 −(i s,q X g ) 2 , and the q-VL can be represented as in Fig. 2(b). V g sin (δ) serves as the reference in this loop. For a given value of δ, a stability criterion, which is similar to the equal-area criterion, can be developed for the q-VL as in Fig. 2(c). A, B, and C are negative-feedback regions while D is a positive-feedback region. If the operating point (OP) exceeds the unstable equilibrium point (UEP) and enters region D, i s,q slides to I max , leading to a large reactive power absorption and a voltage drop. Subsequently, the APC fails to synchronize with the grid. Hence, enhancing damping of the q-VL to minimize the overshoot of i s,q helps to avoid this type of instability. Setting [I q,min , I q,max ] to [−I max , 0] during voltage sags is also beneficial, as this keeps i s,q in regions A and B. This setting might affect the reactive power absorption of the VSG as it tries to keep the reactive current in the injecting region only. However, since there is no need to absorb reactive power during voltage sags, this setting does not impact the VSG reactive current controller during faults.
If M does not intersect V g sin (δ), there is no SEP. Hence, the positive-feedback region, i.e., D, expands to its maximum, as shown in Fig. 2(d), and the q-VL becomes unstable if the OP enters D. As a necessary condition for the q-VL to remain stable is the existence of an SEP, there is no SEP for the OP in the q-VL to converge to. X g can be found via impedance identification or estimated using Thevenin's impedance of the worst-case scenario network. When the q-CL is activated, the following two possible cases can occur.
1) Case A: V q C can regulate v c,q to zero without saturating |i s,q | to I max ; hence, i s,q = i sq,ref and i s,d = I d,max . 2) Case B: V q C cannot regulate v c,q to zero and |i s,q | saturates to I max , leading to i s,d = 0. It is assumed that the VLs (including both d-VL and q-VL) are much faster than the power-angle loop. Besides, even when the q-CL is active, if there exists an SEP in the q-VL and −I max < i s,q < I max at that SEP, the q-VL can operate normally without the antiwindup engagement in this loop. Hence, v c,q can track zero almost instantly due to the high bandwidth of the voltage control loop (Case A). If either of the abovementioned conditions is not satisfied, Case B occurs.
To study the saturation of the q-VL, three ranges for δ where 0 o < δ < 180 o are considered as follows.
1) If 0 o < δ < δ c , as shown in Fig. 2, there is always an SEP existing in the q-VL, with −I max < i s,q < I max . Thus, Case A occurs in this range of δ.  Hence, Case A occurs in this range of δ. Because the VSG is assumed to be unstable almost instantly when δ exceeds δ c , this case is not considered in the P −δ curve in Section III-B. A diagram summarizing the abovementioned discussion is provided in Fig. 3. For the case when −180 o < δ < 0 o , the M curve is flipped to the negative region, i.e., M (i s,q ) = − (I max X g ) 2 −(i s,q X g ) 2 . A similar analysis can be applied for this region of δ. It is worth noting that Case B in this region of δ makes i s,q saturate to −I max .
When δ exceeds δ c , θ VSG starts deviating from θ FM , leading to a nonzero v c,q . The absence of an SEP in the q-VL affects the P −δ curve of the VSG presented in Section III-B. This leads to the end point of the P −δ curve (NV-CLd), as shown in Figs. 4(a) and 5(a). More details about the P −δ curve can be found in Section III-B.

B. P − δ Curve of a q-Prioritized Current-Limited VSG
When the q-CL is activated due to a severe voltage sag, the VSG operates in a current-controlled mode with an output cur- As discussed in Section III-A, Case B results in a failure of the q-VL. Thus, the use of P −δ curve in analyzing the active power control loop in this case is not appropriate. Hence, only Case A is focused on in this study. As the q-VL is much faster than the APC, in this section, q-VL is assumed to be ideal. Thus, v c,q ≈ 0 and θ FM ≈ θ VSG . Hence, the active power is (4) Thus, The UEP of the q-VL occurs at a positive φ sat (i s,q > 0), as shown in Fig. 2. It associates with the second expression in (5). Hence, this expression is not used for deriving the P −δ curve. Assuming that the transmission line is prominently inductive and lossless [1] Plotting (6) against δ with φ sat defined as the first expression in (5) gives the P − δ curve of a q-CL-VSG, i.e., the normalvoltage current-limited (NV-CLd) curve in Fig. 4(a). The UEP of the P −δ curve, which is the intersection between the decreasing side of the P −δ curve (i.e., NV-CLd) and P 0 , is where the positive feedback mode of the power-angle control loop starts [10]. If the OP in this loop exceeds the UEP, the power-angle loop becomes unstable. The normal-voltage (NV)-VC P −δ curve is governed by where V FM approximates V g as the VSG is in the VC mode.
As the OP approaches the intersection point of the NV-CLd and the NV-VC curves, i.e., point 6 in Fig. 4, the capacitor voltage V FM approaches its reference V ref because point 6 belongs to the VC mode. Thus, the d-voltage, i.e., v c,d , also converges to V ref , as v c,q is kept at zero by the q-voltage controller V q C. Hence, the voltage error, i.e., (V ref − v c,d ), fed to the d-voltage controller, i.e., V d C in Fig. 1, reaches zero at point 6. This makes the output of the d-voltage controller, i.e., u v,d in Fig. 1, zero, thanks to the antiwindup and the feedforward term. Hence, i sd,ref equals i * sd,sat , and the d-voltage controller (V d C) exits the saturation mode at point 6. Since V q C does not saturate during the fault recovery, as presented in Section III-A, when the V d C becomes unsaturated at point 6, the VSG can return to a normal VC operation. The recovery of v c,d , which equals |V g ∠θ g + ji sat X g |, is shown in Fig. 4(b). Thus, the q-CL-VSG in this study is not supposed to get stuck in the current-limited mode after fault clearance (FC).

C. Summary of TS of q-CL-VSGs
As presented previously, there are two main causes of instability, given as follows.
1) Cause 1: The positive feedback mode in the power-angle control. In this case, the UEP in the P −δ curve is exceeded. 2) Cause 2: The positive feedback mode in the M −i s,q curve of the q-VL. This case can be categorized into the following two subcases. a) Cause 2.1: There is no SEP existing in the M −i s,q curve of the q-VL [see Fig. 2(d)]. This is when δ > δ c . b) Cause 2.2: There is an SEP existing in the M −i s,q curve of the q-VL, but the OP of the q-VL exceeds the UEP of the q-VL and δ enters region D in Fig. 2(c).

A. Simulation Results
To validate the stability conditions derived previously, three cases, i.e., Cases I, II, and III are tested, with parameters listed in Figs. 4-6. The tested system is shown in Fig. 1. The base voltage and power are 110 kV and 55 MVA, respectively. J and D p are set to 15 and 50 per unit (p.u.), respectively. A three-phase bolted fault occurs at t = 8 s for all cases. In total, three P −δ curves are presented in Figs. 4(a) and 5(a), which are given as follows.
1) NV-VC curve: This curve represents the operating domain of the VSG when the CL is not active and is determined by (7). In a normal operation, e.g., prefault condition, the OP of the power-angle control stays at the SEP, which is the intersection between the increasing side of this curve and P 0 .

2) During-fault current-limited curve (DF-CLd): This curve
shows the operating domain of the OP during faults (or voltage sags). As the CL is activated during faults, this curve is determined by (6) with a low in-fault grid voltage. The OP jumps from the SEP to this curve after the fault occurrence and stays on this curve until the FC. 3) NV-CLd: This curve shows the operating domain of the OP when the grid voltage recovers to its nominal value, but the CL still engages due to power swings. Hence, (6) is used to derive this curve. The intersection between the decreasing side of this curve and P 0 is where the UEP of the power-angle control is. As this study focuses on deriving stability limits of the VSG based on available information about parameters and grid conditions, only the postfault period is focused, although the in-fault process of the VSG is shown in Figs. 4 and 5.
1) Cause 1-Positive-Feedback Mode in the Power-Angle Control: Case I demonstrates the instability of the VSG caused by Cause 1 mentioned in Section III-C. In Fig. 4, the results of Case I are presented. In this case, the parameters are set such that during the angle growth, δ reaches the UEP (of the P −δ curve) before exceeding the end point (or δ c ). In other words, the UEP is on the left-hand side of the end point in the P −δ curve. To obtain this scenario, δ c (or the end point) is pushed to a high value by using a large X g and a high I max according to (3). At the same time, the UEP in the P −δ curve is brought to the left by setting P 0 to a high value, e.g., 0.9 p.u. In Fig. 4(a), the fault occurrence causes the transition from point 1, i.e., the SEP, on the NV-VC P − δ curve, to point 2 on the DF-CLd curve due to the voltage sag and the CL activation. The angle then grows on the DF-CLd curve during the fault until the FC at point 3, i.e., t = 8.167 s. It jumps to point 4, as the grid voltage recovers, then point 5 on the NV-CLd curve. Since the UEP is not exceeded by the OP, the OP comes back to the SEP on the NV-VC curve via point 6. The simulated trajectory validates the correctness of (6). Besides, in Fig. 4(b), increasing the fault clearing time to t = 8.171 s makes δ cross the UEP angle, leading to an unstable response of P VSG and ω VSG in Fig. 4(c).
2) Cause 2.1-No SEP Existing in the M −i s,q Curve of the q-VL: Case II, whose results are shown in Fig. 5, represents the instability caused by Cause 2.1 in Section III-C. Thus, the power-angle control should not enter its positive-feedback region (beyond the UEP in theP −δ curve). In contrast to Case I, in this case, δ reaches the end point (or δ c ) before the P −δ curve (NV-CLd) intersects P 0 . To make this scenario happen, δ c (or the end point) is pushed lower by decreasing X g and I max , compared with Case I, according to (3). Furthermore, the UEP in the P −δ curve is eliminated by reducing P 0 to 0.4 p.u., as shown in Fig. 5(a).
In Fig. 5(a), P 0 does not intersect the decreasing side of the NV-CLd curve. A fault occurs at point 1 and is cleared at point 3. δ then jumps to point 4 and reaches δ c at point 5. Both P VSG and δ collapse afterward. After reaching point 5, δ > δ c . Thus, no SEP of the q-VL exists. As a result, in Fig. 5(b), when i s,q passes zero, the OP enters region D, i.e., positive-feedback mode, in Fig. 2(d), resulting in a rerise of u v,q . i s,q increases to its limit, and the VSG becomes unstable. It is worth noting that v c,q traces in Figs. 4(c) and 5(c) stay close to zero during the transients. They only differ from zero after the VSG becomes unstable. This behavior validates the analysis and assumptions in Section III.
3) Cause 2.2-Excession of the UEP in the M −i s,q Curve of the q-VL: Case III demonstrates the instability caused by Cause 2.2. The results of this case are presented in Fig. 6. To prevent δ from exceeding either the end point (δ c ) or the UEP in the P −δ curve, the APC is frozen when the voltage V FM drops below 0.9 p.u. by setting the pas flag in Fig. 1 to zero. I max and X g are set lower to reduce the height of the M curve, as the maximum of the M curve is I max X g . In addition, P 0 is set to a high value, i.e., 0.93 p.u., to bring V g sin (δ) higher. This moves the UEP in the M −i s,q curve of the q-VL to the left-hand side so that the current trajectory, in this case can exceed this UEP. This case aims to show that, even without any excessive growth in δ, the q-VL can still become unstable due to the positive-feedback mode in this loop. Thus, this validates the analysis developed from the M −i s,q curve.
During the fault, i.e., when the effective grid voltage is 0.1 p.u., δ c approaches 90 o , whereas δ c = 40 o when V g = 1 p.u. In this case, the APC is frozen by setting pas to 0, when a voltage sag is detected. Hence, δ mainly stays around δ i = 34 o , which is the prefault SEP angle, and remains below δ c , as shown in Fig. 6(c). Thus, the existence of an SEP in the q-VL is guaranteed. In this test, a stable case and an unstable case are obtained by adjusting the gains of the V q C, i.e., (K pv , K iv ) = (0.79, 0.2) and (K pv , K iv ) = (0.83, 0.2) for the stable and unstable cases, respectively. Right after the FC, the OPs of the q-VL travel from points 1, which are the in-fault SEPs of the q-VL, to points 3, where |i s | curves saturate again, via points 2. Between points 1 and 3 in Fig. 6(a), as |i s | < I max , as shown in Fig. 6(b), the simulated trajectories in Fig. 6(a) stay below the M curve. As shown in Fig. 6(a), if the trajectory stays on the left-hand side of the estimated UEP, which is the intersection between the M curve and V g sin(δ i ), it can then return to a stable operation (exit the current-limited mode) as the stable trajectory does; otherwise, it enters the positive-feedback mode, as the unstable trajectory does. In the latter, i s,q slides to I max after the FC, leading to the collapse of P VSG shown in Fig. 6(c).

B. Experimental Results
The analysis in Section III is further validated in an experimental setup with the base voltage, base power, J, and D p set to 90 V, 1.5 kVA, 20 p.u., and 35 p.u., respectively. In the setup, the VSG is implemented in an Imperix inverter and connected to a Regatron TC.ACS grid simulator. Parameters of the experiments are shown in Figs. 7-9. In total, three tests in Section IV-A are repeated in the experimental setup with a fault occurrence at t = 0.5 s. Their results are summarized in Figs. 7-9. The ideas behind these cases are exactly the same as those in Section IV-A.
In Fig. 7(a), the power-angle trajectory in Case I validates the P −δ curve derived in (6). The fault occurs at point 1 and is cleared at point 3 when t = 0.68 s. The OP reenters the currentlimited mode at point 4 and starts decelerating at point 5. As the angle at point 5 is below the UEP angle, the OP can exit the current-limited mode at point 6 and stably converge to the SEP, whereas, as shown in Fig. 7(b) and (c), if the angle δ exceeds the UEP angle, the VSG becomes unstable due to the positivefeedback mode in the power-angle loop.
In Case II, whose results are shown in Fig. 8, there is no UEP in the P −δ curve of the VSG, as no intersection between P 0 and the decreasing side of the NV-CLd curve exists. The fault occurs  at point 1. In Fig. 8(a), after the FC at point 3, when t = 0.96 s, the OP evolves to point 4 and then 5. At point 5, δ hits δ c , and the SEP in the q-VL disappears, as elaborated in Section III-A. Eventually, the OP of the q-VL enters region D described in Fig. 2(d). This leads to the divergence of i s,q to I max , as shown in Fig. 8(b), and the collapse of P VSG in Fig. 8(c). As a result, the APC and the whole VSG become unstable, hence triggering the protections of the setup.
In Case III, whose results are summarized in Fig. 9, the APC is frozen during the fault via the pas flag. Thus, δ does not grow and remains at δ i = 37 o , which is below δ c = 46 o in this case. The fault is cleared at t = 0.68 s. As shown in Fig. 9(a), the stable trajectory (blue), with (K pv , K iv ) = (0.4, 1), hits the M curve at a point which is on the left-hand side of the UEP of the q-VL, i.e., region C in Fig. 2(c). Hence, it can recover to a stable operation, whereas, if the trajectory (red), with (K pv and K iv ) = (0.45, 1), exceeds the UEP and enters region D, it diverges to I max as shown in Fig. 9(a) and (b), resulting in the collapse of P VSG as in Fig. 9(c). These eventually trigger the protections, thus isolating the VSG.
The tests in Cases II and III validate the stability criterion of the q-VL established in Section III-A.

V. CONCLUSION
This letter provides insights into the instability mechanisms of q-CL-VSGs. The stability issues are caused by both the APC and the q-VL. The P −δ curve of a q-CL-VSG is first derived to conduct TS analysis of the active power loop. It is then found that the absence of an SEP in the q-VL can occur after a fault, leading to a failure of the VSG. Thus, a stability criterion is developed for the q-VL. The abovementioned findings are beneficial for determining the maximum power angle used to calculate the critical clearing time of a q-CL-VSG. In addition, as extensions of this study, enhancing solutions and tuning guidelines can be built from the abovementioned analysis to improve the stability of a q-CL-VSG.