High-Efficiency Millimeter-Wave Single-Ended and Differential Fundamental Oscillators in CMOS

This paper reports an approach to designing compact high-efficiency millimeter-wave fundamental oscillators operating above the <inline-formula> <tex-math notation="LaTeX">$f_{\text {max}}/2$ </tex-math></inline-formula> of the active device. The approach takes full consideration of the nonlinearity of the active device and the finite quality factor of the passive devices to provide an accurate and optimal oscillator design in terms of the output power and efficiency. The 213-GHz single-ended and differential fundamental oscillators in 65-nm CMOS technology are presented to demonstrate the effectiveness of the proposed method. Using a compact capacitive transformer design, the single-ended oscillator achieves 0.79-mW output power per transistor (16 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>) at 1-V supply and a peak dc-to-RF efficiency of 8.02% (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm{ DD}}=0.80$ </tex-math></inline-formula> V) within a core area of 0.0101 mm<sup>2</sup>, and a measured phase noise of −93.4 dBc/Hz at 1-MHz offset. The differential oscillator exhibits approximately the same performance. A 213-GHz fundamental voltage-controlled oscillator (VCO) with a bulk tuning method is also demonstrated in this paper. The measured peak efficiency of the VCO is 6.02% with a tuning range of 2.3% at 0.6-V supply.


I. INTRODUCTION
T HE millimeter-wave (mmW) and the terahertz (THz) frequency bands have great promise in enabling highperformance communication [1], [2] and sensing [3], [4] systems. The wide bandwidth available at these bands gives higher data rates and greater sensing/imaging precision. In addition, these bands encompass the rotational and vibrational frequencies of many molecules and hold great potential in realizing spectroscopy systems [5], [6].
The small wavelength at mmW/THz frequencies ensures that the antennas could be made very small. Together with the scaling of modern semiconductor technologies, much research has been devoted to designing highly integrated circuits and systems working at these frequencies [7]- [15]. However, the design of a solid-state mmW/THz signal sources with adequate output power and efficiency still remains a challenge due to the limited maximum frequency of oscillation f max .
The f max of the compound semiconductor devices, such as indium phosphide (InP) based heterojuction bipolar transistors (HBTs) and high electron mobility transistors (HEMTs), has approached or exceeded 1 THz [16], [17]. A fundamental oscillator of 330 GHz is reported in an 35-nm InP HEMT process with 0.27 mW output power [18]. Fundamental oscillators fabricated in 0.25-µm InP HBT with f max greater than 800 GHz operate up to 570 GHz while generating -19.2 dBm output power [19]. In the CMOS technology, a fundamental oscillator of 300 GHz is achieved with f max of 380 GHz for 65-nm NMOS device [20]. An output power of -7 dBm is realized for a fundamental 240 GHz oscillator in 32-nm CMOS process [21]. For SiGe HBT technology, a fundamental oscillator of 218-245 GHz is obtained with peak output power of -3.6 dBm and efficiency of 0.81% [9]. A clear trend is that high efficiency power generation becomes much more challenging as we get close to f max due to a lower activity of the active device and a lower quality factor Q of the passives components.
In this paper, we present an accurate approach to designing compact high efficiency fundamental oscillators operating above the f max /2 of the active device. Compared to many existing design methodologies, the proposed design approach takes full consideration of the nonlinearity of the active device and the finite Q of the passive devices to provide an accurate procedure for optimizing the output power of the oscillator. A design example of a 213-GHz single-ended fundamental oscillator in 65-nm CMOS technology is presented to demonstrate the effectiveness of the proposed method. With the use of a compact capacitive transformer, the oscillator achieves 0.79 mW output power per transistor (16 µm) at 1.0 V supply and a 8.02% peak dc-to-RF efficiency within a core area of 0.0101 mm 2 . A differential oscillator is also presented with very similar performance. The measured peak efficiency of the VCO is 6.02% with a tuning rang of 2.3% at 0.6-V supply.

II. A REVIEW OF EXISTING APPROACHES TO MAXIMIZING OSCILLATOR OUTPUT POWER
A theory for maximizing the oscillation output power of an active device based on large-signal network analysis was first introduced in [22], [23] and developed in several subsequent works [12], [13], [24]- [28]. In this section, we provide a brief review of this theory and a discussion of its limitations.
Consider a two-port network as shown in Fig. 1. Let V 1 and V 2 be the complex voltages at port 1 and 2 of the network. A complex voltage gain A is defined as [22], [23] Figure 1. General two-port network described by its large-signal Yparameters. A complex voltage gain can be defined as A = V 2 /V 1 .
where A R and A I are the real and imaginary parts of A, respectively. The net output power (or added power) of the two-port can be found by [22], [23] The optimization of P R can then be performed in terms of A. Since the absolute value of the port voltage and current cannot be analytically determined, several different expressions for the optimal voltage gain A opt have been proposed. For example, (2) was derived under the assumption that |V 1 | is a constant with respect to A [22], where g ij and b ij are real and imaginary parts of the large signal Y-parameters y ij of the active network [23], respectively. Alternatively, (3) was derived assuming that |V 1 ||V 2 | is a constant [23], where k is an arbitrary integer. Both equations have been used recently to design high-efficiency millimeter-wave oscillators [12], [13], [15], [29]. Once A opt is determined for a certain transistor and bias condition, the embedding network can be synthesized. By definition, Considering the real and imaginary parts, (4) contains 4 independent equations. To satisfy this set of equations, 3 reactive components are needed in addition to the load resistance which is the 4 th independent variable. The 3-component Π and T network typologies represent the most general and canonical solutions to this problem (Fig. 2). Herein, we use the lossless Π-network, more specifically Fig. 2(b), as an example to demonstrate how the embedding network is synthesized [24]- [26].
Here, the load G L is connected between the gate and source of the active device. From Kirchhoff's current law, we have For lossless embedding networks, combining (1), (4) and (5), we arrive at the following matrix equation Solving the above equation will produce the desired admittance of the embedding network. The actual inductance/capacitance of the elements can be calculated from the admittance value at the desired oscillation frequency.
We note that the above approach is based on linear network analysis whereas oscillators are inherently nonlinear circuits. As such, it cannot accurately predict A opt . For example, in deriving A opt , there is no clear substantiation that either |V 1 | or |V 1 ||V 2 | must be a constant with respect to A. In reality, neither of these conditions is accurate. In addition, the Yparameters of the active network are a nonlinear function of the voltage and current swing at the input and output terminals. This nonlinearity is influenced by the particular process technology as well as the layout, the bias condition, and the circuit topology of the active network. When the active device is operating above half of f max , a linearization of this nonlinear problem may be appropriate because the amplitude of the harmonic waves are relatively small.
Several important works in high frequency oscillator designs have attempted to address the nonlinear design problem. Among them, [22]- [28] are based on quasi-linear network analysis to synthesize a proper embedding network from the large-signal parameters of the active device. Other works tackled the problem using nonlinear optimization [30], [31] of the terminal voltages and currents. When applied to the design of integrated oscillator operating close to f max , existing methods have been found to produce incorrect (i.e. no oscillation) or sub-optimal designs. The primary reasons for this are an inaccurate extraction procedure of the device parameters and a negligence of the effect of the finite Q of the passive embedding network (more discussion in Section. III-C and Section. III-D). Building upon these existing works, we propose a design methodology that addresses these issues.

III. PROPOSED DESIGN APPROACH TO MAXIMIZING OSCILLATOR OUTPUT POWER A. Large Signal Y-parameters Extraction
Many researchers have recognized that there is a strong link between the designs of nonlinear power amplifiers and oscillators [25], [26], [28], [32], [33]. If we define added power P add of the amplifier as then it is well understood that the P add reaches a peak value P add,max shortly after the output power starts to compress [32]. If P add,max is positive, then it is conceivable that a feedback network can be inserted at the output of the active device to route part of the output power back to the input to form an oscillator. As long as the feedback network provides the same impedance to the input and output of the active device, the device is independent of the external circuit. In this case, P add is simply the output power of the oscillator. It can then be postulated that maximizing oscillator output power is equivalent to maximizing the amplifier P add,max . An iterative process based on source-pull and load-pull techniques can be used to maximize P add,max , as shown in Fig. 3. The process starts with a set of initial values for the input power P in , source impedance Z S , and load impedance Z L . The initial values for Z S and Z L may be set to 50 Ω.
The initial values of P in may be set close to the compression point of the active device. A power sweep is first performed to identify the input power P in,opt at which P add,max is achieved under the current operating condition. Setting P in =P in,opt , several iterations of load-pull and source-pull sweeps may be used to identify the optimal source impedance Z S,opt and load-impedance Z L,opt that maximize P add . A power sweep can then be performed at Z S,opt and Z L,opt for an updated P in,opt . This process can be iterated until P in , Z S , and Z L converge to a set of optimal values (P in,opt , Z S,opt , Z L,opt ) that maximize P add,max .
Once the optimal condition is determined, the large signal Y -parameters can be extracted by the following procedures. • Step 1: Extract the large-signal S-parameter with Z S,opt and Z L,opt at the optimum input power P in,opt . • Step 2: Re-normalize the large-signal S-parameters to a common system impedance Z 0 . • Step 3: Convert the re-normalized large-signal Sparameters to Y-parameters as in a linear network [34]. Because Y -parameters are sensitive to the terminal voltage and current swings, this procedure ensures that they are extracted at the exact operating condition for maximum oscillator output power. Theoretically, the Y -parameters may be directly extracted from a two-port measurement at the optimal condition. However, going through the large-signal Sparameter extraction is often easier, whether it's done through circuit simulations, as most high-frequency CAD programs come with built-in S-parameter and source/load-pull tools, or through measurement of an actual device, particularly at high frequencies. In contrast, directly obtaining the optimal terminal voltages and currents may be difficult in measurements [30], [31].

B. Optimal Voltage Gain A opt with Lossless Embedding Networks
Once the large-signal Y -parameters, Z S,opt , and Z L,opt are determined, A opt can be calculated. Consider a terminated two-port network as shown in Fig. 4.
The port voltages and currents satisfy Solving (7) gives the complex voltage gain A Therefore, Alternatively, the input admittance of the two-port with Y L as the load is given by When maximum added power is achieved,  Figure 4. Two-port network with terminated loads.
Therefore, A opt can also be obtained using Furthermore, if the source/load-pull is performed in a circuit simulator, A opt may be directly obtained from its definition, i.e. dividing V 2 by V 1 .
(8) and (9) give practically identical value for A opt . To illustrate this, we show the simulated and the calculated output power profile in Fig. 5(a). For each A, an automated script calculates the component values of the feedback network using (6), and constructs the netlist for the oscillator circuit. The script then runs a periodic steady state simulation on the netlist to find the output power of the oscillator. It can be seen that existing design equations deviate from the optimal solution, and that the A opt calculated from our design method is almost identical to the optimal value produced by bruteforce search. The plot is generated by circuit simulation. In these simulations, a lossless embedding network is assumed. Later we will see that practical lossy embedding network will introduce further design errors that existing design techniques do not take into account.

C. Synthesis of Embedding Networks with Finite Q
In integrated circuit processes, on-chip passive components typically have fairly low Q due to resistive loss of the metal interconnects and dielectric loss of the substrate. For practical designs, it is imperative that the Q of the feedback network components be taken into account in the design process. In this section, we use Π-embedding networks as an example to illustrate how component Q could affect the embedding network design.
For Π-embedding networks, the admittance parameters should be used. A lossy inductor or capacitor can be modeled as a lossless reactive component in parallel with a resistor and Q is defined as We first consider the case where load G L is connected at the gate. G L in (6) is then split into load conductance and the conductance of Y 1 : Unit: mW Unit: mW Figure 5. Constant power contours with respect to real and imaginary part of the complex voltage gain A, where A = A R +jA I for (a) lossless Π-embedding network and (b) lossy Π-embedding network with quality factor for capacitor and inductor of 50 and 30, respectively. In (a), the dashed circuit represents the boundary between oscillation and no oscillation. In (b), it is observed that the oscillation region significantly shrinks and that the output power is much more sensitive to Aopt than in the lossless case. (c) plots the trajectory of Aopt of an example particle swarm optimization scheme to reach the true Aopt with finite Q.
The oscillation condition can then be expressed in the following matrix form: where The subscript i denotes where the load is connected, with 1 representing the case when the load is between the gate and the source, 2 between the drain and source, and 3 between the gate and the drain. Following the same procedure, we can obtain the design equations when load is connected drain-source and gate-drain. The right hand side of (10) remains the same.
The design equations are linear with respect to the unknowns which can be easily solved as is the case when embedding is lossless. G Qi (i = 1, 2, 3) should always be a positive value because it represents the conductance of reactive elements. Therefore, as the reactance of an inductor is negative, the associated Q should also be negative to make sure G Qi (i = 1, 2, 3) is positive.
However, the type of passive element cannot be predetermined without solving the equations. It is necessary to enumerate all eight possible combinations of the embedding: either capacitor or inductor for each of the three components. Each combination presets the sign of Q, and the solved susceptance should satisfy to filter out networks with negative conductance components.
The impact of Q on oscillator output power is different for the three reactive components. Fig. 6 shows the simulated oscillator output power with respect to the component Q. Each curve represents one lossy component whose Q is swept from 10 to 100 while the others are kept ideal. It can be seen that the Q of Y 3 affects output power most significantly whereas Q of Y 1 and Y 2 have negligible influence on power when they are greater than 40. This is due to the larger voltage swing between  Q2 Q3 the gate and drain terminals. The difference in sensitivity to Q imposes a greater concern on the implementation of Y 3 . It also affects the oscillator topology and physical realization which will be discussed in Section IV.

D. A opt with Finite Q
It should be noted that A opt will deviate from the ideal value given by (8) or (9) when the loss of the feedback network is considered because the lossy network elements consume a fraction of the output power from the active device and maximizing P add,max no longer ensures maximizing output power to the load. This is one of the reasons why existing design approaches fail for integrated devices working close to f max . To illustrate this, we present in Fig. 5(a) and (b) a comparison between the simulated output power with respect to A for lossless and lossy embeddings. Fig. 5(b) is generated in a similar fashion as Fig. 5(a), except that (10) is used in place of (6). It can be observed that the oscillation region, defined as the range of A I and A R that produce a positive output power, significantly shrinks with decreasing Q and that the output power is much more sensitive to A than in the lossless case. In this particular example, it is evident that the "ideal" A opt with lossless embedding is sitting at the boundary of the oscillation region. In an actual implementation, no output may be observed due to the loss of the output matching network.
In practical designs, the "true" A opt with finite Q can be obtained by either searching around the original A opt value or numerical optimization. We present here a possible optimization approach based on particle swarm optimization (PSO) [35], [36]. PSO solves an optimization problem by having a collection of possible solutions, referred to as "particles", and moving them in the search-space according to the their position and velocity. Because PSO does not require the gradient to operate, it is particularly suitable for circuit optimization problems involving a simulator in the loop.
In this example, two particles are used as our studies show that increasing the number of particles does not result in better solutions. The particles are initialized at the "ideal" A opt value given by lossless embedding networks and given random initial velocities. In each iteration, the output power of the resulting oscillator is simulated for each particle and is used as the fitness function, based on which the individually best particle pBest and the globally best particle gBest are recorded. Each particle is then updated by moving towards pBest and gBest. These steps are repeated until the fitness difference between two consecutive pBest is less than a predefined error value. Fig. 5(c) shows the trajectory of the gBest particle that leads to the global optimum. The convergence to the optimum point is very reliable.
Lastly, we should also note that when finite Q is considered, the voltage swing at the input and output port of the active device may change from the lossless embedding case, thus leading to a change in the device large signal Y-parameters. To resolve this issue, the Y-parameters may need to be reextracted at a different input power and iterated through the design process.

E. Influence of Harmonic Impedance
Harmonic load impedance in general has an effect on fundamental output power and efficiency. However, when oscillation frequency approaches f max /2 or even higher, the influence of harmonic termination becomes very small. To illustrate this, we simulated the P add,max and PAE of a 16-µm NMOS transistor under various harmonic terminations. The results are presented in Table I. We notice that optimal second harmonic termination has minimal effects on the fundamental output, with a 5.46% increase (1.93 mW vs. 1.83 mW) in maximum added power and 5.32% increase (17.23% vs. 16.36%) in maximum PAE. Third order harmonic has even less effect with less than 0.3% difference between optimum and worst termination impedance. These improvement in the fundamental power will be further negated by the loss of additional harmonic matching networks. As will be shown later in this paper, loss of passive components has a significant impact on the oscillation power. As such, we choose not to consider harmonic impedance terminations in this work.

IV. DESIGN EXAMPLES
To demonstrate the validity and effectiveness of the above design approach, we present example designs for highefficiency 215 GHz fundamental-mode single-ended and differential oscillators, and a fundamental-mode voltage controlled oscillator (VCO) in a 65-nm CMOS technology.

A. Process and Transistor
In this work, we realize our design in a 65-nm CMOS technology featuring 9 metal interconnect layers ( Fig. 7(a)).
To achieve a high f max , we custom lay out a 16-µm NMOS transistor, as shown in Fig. 7(b). This transistor is constructed using two parallel 8-µm NMOS transistors. Double gate contacts are used to increase f max by reducing the gate resistance. A 3-D rendition of the interconnects to the transistor is shown in Fig. 7(c). The parasitics of this 16-µm NMOS transistor are extracted up to M7 by Calibre and the simulated f max is around 398 GHz.
B. Oscillator Topology 1) Choice of Load Position: Theoretically, all six topologies, as shown in Fig. 2, should generate the same output power with lossless embedding components. In practice, however, not all topologies are equal, particularly in terms of the load impedance matching.
Take lossless Π-networks for example, the output power extracted from the three networks are: Replacing V 2 as A opt · V 1 , and recalling that power in (14) are identical, the ratio of loads are obtained: From (15) we see that the ratio of G L1 over G L2 depends on the magnitude of A opt . For the transistor size and biasing condition in this design, the magnitude of A opt is 0.89, making G L1 and G L2 fairly close to each other. G L3 , however, is almost always several times smaller than G L1 due to real part of A opt being always less than zero. Too large a load resistance makes it difficult to match with low loss. The component values for the oscillator with lossless and lossy embedding networks are summarized in Table II and Table III for a more  quantitative comparison. Between the cases of gate-source connection and drainsource connection, we note that the drain-source connection results in a network with two large inductors and is therefore less preferable. Therefore, we choose to place the load at the gate of the active device in this design. The final values of the components (caption of Fig. 8) are slightly different from Table III to take into account the parasitics of the components.
2) Biasing Topology: The gate and drain terminals of the active device could be biased at either the same voltage or separately. The advantage of separate biasing is that oscillating power and efficiency can be optimized independently. However, as the calculated Y 3 (Fig. 6) is an inductor, a large capacitor is required in series to allow different gate-drain dc voltage. This capacitor degrades the overall Q of Y 3 in two ways: 1) the loss on the capacitor alone is considerable due to inability to build large high-Q capacitors (e.g. above 150 fF) at millimeter wave frequency; and 2) the series capacitor inevitably reduces the overall inductance so that to maintain the effective inductance unchanged, the inductor value has to be increased which in turn adds additional loss to the embedding network. Therefore, the biasing of the gate and the drain are shared in our design to achieve a compact die area.
The evolution of the circuit topology is captured in Fig. 8. Note that we take advantage of the parallel connection between R 1 and C 1 , and utilize a capacitive transformer to match a typical system impedance of 50 Ω to the calculated optimum load, as shown in Fig. 8(b) [29].

C. Differential Oscillator
A differential oscillator is derived from the single-ended oscillator by locking two of them 180 • out-of-phase through the drain capacitor C 3 , as shown in Fig. 8(c). With C 3 = 0.5C 2 , each half of the differential oscillator maintains the optimal oscillation condition. In the common mode half circuit, C 2 is left open and in this specific example, the remaining two reactive component (L 1 & C 1 ) do not provide an oscillation condition. Therefore, the two oscillator cores can only oscillate in the differential mode.

D. Voltage Controlled Oscillator (VCO)
Based on the proposed optimal design approach, we also present a voltage controlled oscillator design with high output power and dc-to-RF efficiency across the tuning range. Frequency tuning of integrated oscillators is commonly achieved by using varactors. At millimeter-wave and THz frequencies, the quality factor of a varactor in CMOS process is quite low, resulting in low output power and efficiency.
To overcome this limitation, we realize frequency tuning by varying the MOS transistor bulk voltage, as shown in Fig. 8(d). Here, the MOS transistor's bulk is isolated by a deep n-well. As the bulk voltage increases, the parasitic capacitance of the MOS transistor becomes large due to decrease in depletion region width. R T is used to limit dc current when tuning voltage V T is high (> 0.8 V) [37]. Compared with the varactor tuning method , bulk voltage tuning causes less degradation of the quality factor of the oscillating tank.

E. Passives
In order to achieve a better Q, the top metal layer (M9) is used to realize the inductor and ground metal beneath the inductor is removed. The spiral inductor with inner diameter 20 µm and width 4 µm is shown in Fig. 9 together with the corresponding effective inductance L and Q. At 215 GHz, the calculated inductance L is 33.6 pH and the qualify factor Q is 28.3.
Metal 6 and metal 7 layers are used to form parallel-plate capacitors for higher capacitance density and quality factor. The capacitance and Q of an example capacitor with size  Fig. 10. At 215 GHz, the calculated capacitance is 17.9 fF and Q is 44.1.

F. Measurement Results
The measurement setups for measuring output spectrum, phase noise and output power are shown in Fig. 11. The output spectrum and phase noise of oscillators are measured using a signal analyzer (Agilent N9030A) with an external frequency extender (VDI WR-5.1 TX and RX mm-head module) ( Fig. 11(a)). The LO signal which is generated from signal analyzer is fed into a tripler (PMP Ka3) through a diplexer (OML DPL313B) and then into the LO input port of the frequency extender. After multiplied by 18 times and amplified, the LO signal is mixed with the output signal of oscillator and the amplified IF signal is fed back to signal analyzer through the diplexer. A WR-5 bend is connected between the frequency extender and the G-band probe. The oscillators are biased through a dc probe. LDO regulators powered by batteries are used to provide the V DD supply voltage to the oscillators. The combination of the battery supply and LDO ensures that minimal supply noise is upconverted to the carrier frequency. Pictures of the fabricated circuit dies are shown in Fig. 12. The die size is 0.26 mm×0.26 mm for the single-ended oscillator ( Fig. 12(a)) and 0.37 mm×0.24 mm for the differential oscillator ( Fig. 12(b)). Due to the use of the capacitive transformer, the core size of the single-ended oscillator is 0.0101 mm 2 . Fig. 13 shows the measured output power, dc-to-RF efficiency, and phase noise of the single-ended and differential oscillators. The output power of the single-ended oscillator is measured with an Erickson PM4 calorimeter, as shown in Fig. 11(b). With a dc current of 11.5 mA from a 1.0 V drain voltage, the oscillator achieves a 0.79 mW output power. For the single-ended oscillator, as shown in Fig. 13 (a-c), the measured output power increases monotonically with V DD with a peak dc-to-RF efficiency of 8.02% at a V DD of 0.80 V.  At 1.0-V supply, the single-ended oscillator achieves a dcto-RF efficiency of 6.87%. The measured phase noise is -93.4 dBc/Hz at 1 MHz offset and -114.9 dBc/Hz at 10 MHz offset, as shown in Fig. 13(c). Fig. 14 shows the measured IF spectrum of the single-ended oscillator. The measured oscillation frequency is 213.18 GHz and deviates from the design target (215 GHz) by approximately 1%. To measure the differential oscillator, both the spectrum analyzer and the power meter are connected to provide 50-Ω terminations to both ports. The measured oscillation frequency of the differential oscillator is 213.32 GHz, which is also close to the design target (215 GHz). The measured output power, dc-to-RF efficiency, and phase noise of the differential oscillator are shown in Fig. 13 (d-f). The measured total output power is 1.618 mW and the measured efficiency is 6.86% at a V DD of 1.0 V. The peak efficiency is 8.00% at a V DD of 0.65 V. The measured power may potentially be lower than the actual power because of the impedance imbalance of the measurement setup. The measured phase noise of the differential oscillator is -90.9 dBc/Hz at 1 MHz offset and -112.6 dBc/Hz at 10 MHz offset.
The measured output frequency, output power, dc-to-RF efficieny, and phase noise of the 213 GHz fundamental VCO are shown in Fig. 15. The tuning profile of the VCO is shown in Fig. 15(a). At a V DD of 0.6 V, its oscillation frequency is tuned from 211.0 GHz to 215.9 GHz with bulk voltage swept from 0 V to 1.0 V. The measured output power varies from -0.83 dBm to -7.9 dBm and -6.8 dBm to -14.5 dBm at a drain voltage of 1.0 V and 0.6 V, respectively, as shown in Fig. 15(b). Although the output power is much lower than the highest output power possible, we note that the VCO maintains high power efficiency of better than 6% over the tuning range ( Fig. 15(c)). We also note that for bulk voltage less than 0.8 V, the variation in output power is less than 1.2 dB for V DD = 1.0 V and less than 2.1 dB for V DD = 0.6 V. The measured phase noise is -93.7 dBc/Hz at 1 MHz offset and -114.5 dBc/Hz at 10 MHz offset, as shown in Fig. 15(d).
The discrepancy between the design target, simulation, and measurement may be due to a number of factors, including inaccurate device modeling provided by the foundry, fabrication tolerances, and small errors introduced in the electromagnetic simulation of the passive structures (e.g. the slopes of the sidewalls of the interconnect traces modeled as perfectly vertical sidewalls, and groups of vias simplified to a slab of metallic connection). Table IV compares the designed oscillators with the state-of-the-art and shows clearly the advantages of our proposed design in terms of efficiency and area.

V. CONCLUSION
In this paper, we have presented an accurate design approach that maximizes the output power and dc-to-RF efficiency of integrated fundamental oscillators working above the f max /2 of the active device. The approach uses sourcepull and load-pull simulations/measurements to determine the optimal source impedance, load impedance, and input power presented to the active device such that maximum oscillator output power is achieved. Compared with existing works, the proposed approach takes into account the inherent nonlinear characteristics of the active device as well as the finite Q of the external components, and provides an accurate prediction of the oscillation condition, frequency, and power. To demonstrate the effectiveness of this approach, we have presented a 213 GHz single-ended fundamental oscillator, a 213 GHz differential fundamental oscillator, and a 213 GHz fundamental VCO, all implemented in 65-nm CMOS technology. With the use of compact capacitive transformers, these oscillators achieve smaller area compared to other oscillators.