Flip-Chip Bonding for SiC Integrated Circuits With Gold Stud Bumps for High Temperature Up To 600 °C Applications

This work studies a 3-D stacking approach to silicon carbide (SiC) integrated circuit (IC) chips using flip-chip technology with gold (Au) stud bumps for high-temperature (up to 600 °C) applications. Standard photolithography, sputtering deposition, and lift-off process were used for chip metallization and patterning with titanium (Ti), tantalum silicide (TaSi2), platinum (Pt), and Au thin films. Au stud bumps were used to bond the SiC dummy chips with a flip-chip die bonder. Die shear tests were conducted, and the electric resistance of the daisy chain interconnect between the chips was measured before and after thermal aging in the air at 600 °C for up to 12 days. It is found that the electric resistance of the daisy chain interconnects decreases and stabilizes at about $1 \Omega $ for 36 bumps, showing that the thermal aging process improves the electric performance of the interconnect with Au stud bump bonding by reflowing and annealing the metals. The destructive die shear test shows that, with thermal aging, the shear force decreases for the chip stacks and stabilizes at about 15 gram force (gf) per bump with the TaSi2 diffusion barrier in the metallization. In contrast, the shear strength increases for the chip stacks without the TaSi2 barrier in the metallization.

In this research of flip-chip bonding for 3-D SiC IC integration and packaging, Au stud bump technology was chosen to meet the need for Pt and Au metallization in the high-temperature SiC ICs.Three rounds of experimental work have been completed.Some preliminary research work in the first and second rounds was presented in 2023 IEEE Workshop on Microelectronics and Electron Devices (WMED) [25].This article focuses on the third round, with the first two rounds briefly explained and compared.The major difference between Round 3 and Rounds 1 and 2 is the addition of a tantalum silicide (TaSi 2 ) diffusion barrier layer between Ti and Pt to avoid the diffusion of O 2 and Au (from Au stud bump to Au bond wire) to Ti and SiC ICs underneath [26], [27].Also in Round 3, the bumped dummy chips were treated with argon (Ar) plasma before the chip bonding process.Round 1 gave a preliminary mechanical reliability measurement of the flip-chip bonds in the thermal aging process but no electrical test was done.Round 2 failed in both electrical and mechanical measurements because of the excessive thick (1 µm) of sputtered Pt and Au compared to 300 nm in Rounds 1 and 3.
This article is organized as follows.In Section II, the Round 3 experimental approach is described in detail, which is similar to that of the first two rounds.Section III presents and discusses the measurement results and observations in Round 3 experiment, with the results from Rounds 1 and 2 compared.This article concludes in Section IV.II.EXPERIMENTAL PROCESS Fig. 1 shows a schematic of the metal-to-metal flip-chip bonding process for SiC chips based on Au stud bumping using a wire bonder.Fig. 2 shows a schematic of the flip-chip assembly with a daisy chain interconnect for electric resistance measurements.In brief, the top chip (daughter chip) with Au stud bumps is flipped over and bonded to the bottom (mother) chip or ceramic substrate to make daisy chain interconnections, the top chip is then die-sheared, and the daisy chain electric resistance is measured before and after the thermal aging process at 600 • C.

A. Dummy SiC Chip and Substrate Preparation
SiC dummy chips were made using 4-in double-side polished N-type 4H-SiC wafers of 325 µm thickness.The process is similar to that in [8].The wafers were first cleaned using a buffered oxide etch (BOE) solution for 15 min to remove the surface oxide.
Standard photolithography, sputtering, and liftoff processes were used for the metal pad patterning.A 285-µm-thick Futurrex NR9-3000PY negative photoresist was spun on the SiC wafers by a CEE Apogee spin coater at 3000 r/min for 40 s and exposed using an ABM Semiauto Mask Aligner System at 365-nm wavelength with an exposure energy of 360 mJ/cm 2 .The photoresist was developed in AZ10 for 30 s. Evatec LLS EVO Sputter System was then used to deposit thin film metals onto one side of the SiC wafers.The 100-nm Ti was sputtered onto the SiC wafers as an adhesion layer, followed by 200-nm TaSi 2 as the diffusion barrier layer to prevent Pt/Au from diffusing to Ti and SiC to deteriorate the device performance [27], [28].The wafers were then sputtered with 300-nm Pt, some of which were followed by 300-nm Au.The resist was then removed in acetone overnight.After the lift-off process, the wafers were annealed at 380 • C for 90 s using an AccuThermo AW 610M rapid thermal processing (RTP) system.The wafers were then diced into 3 × 3 mm dummy daughter chips or about 1 × 1 cm mother chips/substrates using a Disco DAD 321 Dicing Saw.
Fig. 3 shows a photograph of part of a completed wafer showing dummy daughter chips and mother chips with different metallization before wafer dicing.The smaller metal pads are 200 µm wide and 600 µm long for Au stud bumping, and the large pads are for the ease of electric measurements.
As a comparison to SiC dummy substrate mother chips with Ti/TaSi 2 /Pt/Au thin film metallization, SiC mother chips with electroplated Au were also prepared.After Ti/TaSi 2 /Pt/Au sputtering, the SiC wafer was electroplated with 10-µm-thick Au using a potassium dicyanoaurate KAu(CN)2 electroplating bath (Technic PUR-A-GOLD 401).The wafer was then diced into about 1 × 1 cm square mother chips.

B. Au Stud Bump Formation and Coining Process
To improve the adhesion of the Au stud bumps to the metal pads, the dummy SiC chips were treated with a 75-W 13.56-MHz PIE Tergo Plasma Cleaner with Ar plasma for 5 min [29].After plasma cleaning, a K&S 4524AD Multiprocess Auto Step Back Ball Bonder was used to form Au stud bumps on the metal pads of the dummy chips with 1-mil Au wire.Fig. 4 shows a micrograph of SiC dummy chips before and after Au stud bump formation on the metal pads.
A coining (flattening) process was carried out to flatten the sharp tail of the stud bumps to improve the flip-chip bonding quality.The coining was done by a FineTech FinePlacer Pico Multipurpose Die Bonder with 1 Newton (N) per bump at 40 • C to flatten the tail of the bumps.A 3-in silicon wafer was used as the "substrate" for the coining process.Fig. 5  shows the micrographs of a metal pad with two Au stud bumps on each end before and after the coining process, showing the flattened stud bumps after the coining process.Fig. 6(a) shows the scanning electron microscopy (SEM) image of a Au stud bump at a tilt angle of 35 • before the coining process using a Carl Zeiss Supra 35VA SEM.The stud bump had a bond ball diameter of about 80 µm, and the bond ball and shoulder's heights were both about 20 µm.Fig. 6(b) shows a typical Au stud bump after the coining process, with an increased ball diameter of about 90 µm and shoulder diameter of about 50 µm.

C. Flip-Chip Bonding
The FineTech FinePlacer Pico Multipurpose Die Bonder was used for flip-chip bonding.The bonding was done with thermocompression (TC) mode, with a bonding force of 1 N/bump (500 MPa for a typical shoulder diameter of 50 µm) and at a bonding temperature of 350 • C for 30 s [24], [30], or thermosonic (TS) mode with a bonding force of 0.5 N/bump (250 MPa/bump) at 150 • C for 0.2 s under an ultrasonic power of 300 mW.Fig. 7 shows a 3 × 3 mm daughter chip bonded on top of a 1 × 1 cm mother substrate chip and a side view of the bonding.The metal pads at the bottom of the top chip can be clearly seen underneath the chip because of the transparency of the N-type 4H-SiC.

D. Thermal Aging Process
After a preliminary die shear and electrical test of the bonded chip stacks, which will be discussed in Section III, the chip stacks were subjected to thermal aging processes in a Fisher 750 Programmable Muffle Furnace filled with laboratory air at 600 • C for up to 12 days to simulate the high-temperature Venus surface environment.

A. Electrical Resistance Measurement
As schematically shown in Fig. 2, a daisy chain interconnect should be formed between the two large metal pads on the mother chip, including all small metal pads and the Au stud bumps.A Siglent SMD 3055 Digital Multimeter was used to measure the daisy chain interconnect resistance before and after thermal aging.The measurement was conducted for four cases.
1) Ti/TaSi 2 /Pt metallized SiC daughter chip flip-chip bonded to the mother chip with Ti/TaSi 2 /Pt/Au metallization using TC bonding.This stack is coded as Pt-Au-TC.2) Ti/TaSi 2 /Pt/Au metallized SiC daughter chip flip-chip bonded to the mother chip with Ti/TaSi 2 /Pt/Au metallization using TC bonding, coded as Au-Au-TC.

TABLE I METALLIZATION AND BONDING CONDITIONS OF FLIP-CHIP BONDED CHIP STACKS FOR ELECTRIC RESISTANCE MEASUREMENT
3) A second Ti/TaSi 2 /Pt/Au metallized SiC daughter chip flip-chip bonded to the mother chip with Ti/TaSi 2 /Pt/Au metallization using TC bonding, coded as Au-Au-TC_2.4) Ti/TaSi 2 /Pt/Au metallized SiC daughter chip flip-chip bonded to the mother chip with Ti/TaSi 2 /Pt/Au metallization using TS bonding, coded as Au-Au-TS.The metallization and bonding conditions of these four cases are listed in Table I.The measured resistance is listed in Table II and plotted in Fig. 8.
For the two cases of Au-Au-TC interconnect, the resistance increased after two days of thermal aging and then decreased Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

TABLE II DAISY CHAIN INTERCONNECT RESISTANCE (UNIT )
Fig. 8. Electric resistance the daisy chain interconnects as a function of thermal aging days.

TABLE III THIN FILM RESISTIVITY AND GEOMETRY FOR RESISTANCE ESTIMATION
and stabilized at about 1 after thermal aging of 4, 6, 8, 10, and 12 days, indicating an improved electric conduction performance of the daisy chain interconnect after thermal aging.This is due to the thermal aging process's reflowing and annealing effect.
For the other two cases, Pt-Au-TC and Au-Au-TS, a considerable resistance of 20 and 40 k was measured before the thermal aging process, indicating a poor connection within the structure.It should be noted that poor electrical contact of even one bump can lead to the electrical degradation of the whole daisy chain interconnect.Fortunately, the thermal aging process annealed and repaired the poor contact.The resistance showed the same trend as Au-Au-TC cases, i.e., decreasing and stabilizing at 1 after thermal aging.
The ideal resistance of the daisy chain can be estimated using the geometry and material properties of the thin films, as listed in Table III.The resistance is estimated to be 9 for the daisy chain Au-Au interconnect, which is close to the measured resistance before thermal aging.The resistance of the Au stud bump is estimated to be 5 m with a ball height of 20 µm and a diameter of 100 µm, which is rather small compared to the thin film interconnect resistance and can be omitted.The decrease in the resistance after thermal aging can be attributed to the high-temperature thermal annealing of metal thin films [31], [32] and the leakage through the SiC substrate.

B. Die Shear Test
Destructive die shear tests were conducted with an XYZTEC Condor 70 Wire Pull and Die Shear Tester before and after the thermal aging process.SEM images for the metal pads of the top chip and bottom chip of the Pt-Au-TC stack and bottom chip of the Au-Au-TC stack as described in Section III-A are shown in Fig. 9(a)-(c), respectively.Fig. 9(a) shows the uniformly flattened surface of the Au stud bumps due to the coining process even though there is no apparent sign for a firm contact between the Au stud bumps and the metal pad on the utmost bottom right corner in Fig. 9(b).In contrast, Fig. 9(c) indicates a firm contact between all the Au stud bumps and the metal pads of the bottom chip of the Au-Au-TC stack.This explains the substantial resistance of 20 and 40 k for Pt-Au-TC and Au-Au-TS chip stacks before the thermal aging process in comparison to the smaller resistance of 10 for the Au-Au-TC and Au-Au-TC_2 stacks.
To test the mechanical reliability, six groups of chip stacks were made and tested with the die shear tester in this Round 3 experiment.The metallization and bonding conditions are listed in Table IV.As a comparison, experimental Rounds 1 and 2 of the research described in [25] are also listed in Table IV.The destructive die shear test results are listed in Table V.As stated in Section I, the major difference between Round 3 and the first two rounds was the addition of the TaSi 2 diffusion barrier layer.
In Round 2, despite the interdiffusion between Ti and Pt or Au, the bond strength decreased after thermal aging because of the cracking of the metals due to the thermal stress induced by the sputtered thick Au or Pt film of 1 µm, as shown in the SEM image in Fig. 10.
In Round 3 of the experiment that this article is focused on, for TC mode, the destructive die shear force was measured to be about 50 and 100 gram force (gf)/bump before thermal aging.This is significantly (several times) greater than that of measurement in Rounds 1 and 2 because of the Ar plasma treatment of the metal surface in Round 3. The large difference  The bond strength of the chip stacks in TS mode is much smaller than the TC mode and comparable to the TS mode in Round 2. This is because of the decreased ultrasonic power,   During thermal aging, the bond strength decreased for the chip stacks in Round No. 3 and stabilized at about 15 gf/bump for TC mode and about 6 gf/bump for TS mode.In contrast, for Round No. 1, the interdiffusion between Ti and Pt or Au increased the die shear force during the thermal aging process, which can be clearly seen in Fig. 12.This is likely because the TaSi 2 diffusion barrier blocks the diffusion between Ti and Pt/Au.The cracking of the Au stud bumps during thermal aging may also contribute to the decrease in the bonding strength.
A Thermo Scientific Noran System 7 X-ray Microanalysis system was used for energy-dispersive X-ray spectroscopy (EDS) analysis.SEM and EDS analyses show that a common failure mode in the die shear test was bump (ball) lift.Figs. 13 and 14 show the EDS analysis of a crater after the ball bump was lifted for cases Pt-Pt-TC3 (Round 3) after eight days of thermal aging and Au-Ep-TC1 (Round 1) after six days of thermal aging, respectively.The crater in Fig. 13 exposed Pt 2 Si [28], while the crater in Fig. 14 exposed SiC.The difference indicates that TaSi 2 effectively blocked the interdiffusion between Pt and Ti in Round 3 chip stacks.This also explains different trends of die shear force change after thermal aging with and without the TaSi 2 diffusion barrier layer in the metallization.
From Table V and Fig. 12, it can also be seen that there is no significant difference in the mechanical reliability between Pt and Pt/Au metallization during thermal aging, even with electroplated Au for metallization.

IV. CONCLUSION
Experiments were conducted for Au stud bump-based flipchip bonding of SiC chips for high-temperature applications up to 600 • C. Ar plasma cleaning of the metal surface significantly improves the flip-chip bonding strength.The high-temperature environment in the thermal aging process reflows and anneals the thin film metals, which improves the electric conductivity of the thin film interconnect.In contrast, the resistance of the Au stud bumps is negligible.Thus, flipchip bonding substantially decreases the electric resistance in high-temperature SiC chip packaging compared to the wirebonding method.With the TaSi 2 diffusion barrier in the thin film metallization, the destructive die-shear force of the Au stud bumps between the chips decreases and stabilizes at about 15 gf per bump, likely because the TaSi 2 blocks the interdiffusion between Ti and Pt, and the bond between Ti and Pt is weaker than between SiC and Ti.To meet the minimum die attach strength requirement of 2.5 kgf set by "MIL-STD-883 method 2019.9-Dieshear strength" [33], about 166 Au stud bumps are needed for a chip without the assistance of package sealing and encapsulation.Between Pt and Pt/Au metallization for ohmic contact, there is no significant difference concerning the electrical and mechanical performance during thermal aging.Simple Pt metallization is recommended for the flip-chip bonding process.This study shows the great potential for flip-chip technology to be used in the SiC IC packaging for high-temperature (up to 600 • C) applications, such as the electronic system of Venus surface landers.

Fig. 2 .
Fig. 2. Schematic of flip-chip assembly with daisy chain interconnect between two large bottom pads: (a) 2-D structure before flip-chip bonding and (b) 3-D structure after flip-chip bonding, with Au stud bumps between top pads and bottom pads (not shown).

Fig. 4 .
Fig. 4. Micrograph of SiC dummy chips before (left) and after (right) Au stud bumps were formed on the metal pads of SiC chips.

Fig. 5 .
Fig. 5. Micrographs of Au stud bumps on metal pads before (top, with a sharp tail) and after (bottom, with a flat surface) flattening processes.

Fig. 6 .
Fig. 6.SEM image of: (a) typical Au stud bump with a tail and (b) Au stud bump after coining with the flattened surface.

Fig. 7 .
Fig. 7. (a) Photograph of a SiC dummy daughter chip flip-chip bonded to a SiC dummy mother chip.(b) Optical micrograph of side view of the flip-chip bond showing six compressed Au stud bumps close to the edge of the chip.

Fig. 9 .
Fig. 9. SEM images for the metal pads of: (a) top chip of the Pt-Au-TC chip stack; (b) bottom chip of the Pt-Au-TC chip stack; and (c) bottom chip of the Au-Au-TC chip stack, after 12 days of thermal aging at 600 • C.

Fig. 10 .
Fig. 10.SEM image of metal pads of a Round 2 chip after thermal aging and die shear, showing the cracking of the metal layers.

Fig. 11 .
Fig. 11.SEM image of: (a) top chip of the flip-chip stack code Au-Au-TC3-0 with a bond strength of 104.60 gf/bump and (b) that of code Pt-Ep-TC3-0 with a bond strength of 50.16 gf/bump.(c) Flat "coin" bump in (a).(d) Nonflattened bump after chip bonding in (b).

Fig. 12 .
Fig. 12.Comparison of die shear test results between Round 1 without TaSi 2 and Round 3 with TaSi 2 diffusion barrier in the metallization.

Fig. 13 .
Fig. 13.(a) SEM and (b) EDS of Pt-Pt-TC3 top chip with a bump detached after die shear after eight days of thermal aging.

Fig. 14 .
Fig. 14.(a) SEM and (b) EDS of Au-Ep-TC top chip with a bump detached after die shear after six days of thermal aging.

TABLE IV METALLIZATION
AND BONDING CONDITIONS OF FLIP-CHIP BONDED CHIP STACKS FOR DIE SHEAR TEST

TABLE V DESTRUCTIVE
DIE SHEAR FORCE PER BUMP BEFORE AND AFTER THERMAL AGING (UNIT: gf)