Complementary Resistive Switching in ZnO/Al2O3 Bi-Layer Devices

This paper reports the complementary resistive switching (CRS) characteristics exhibited by Au/ZnO/Al2O3/ Fluorine doped tin oxide (FTO) bilayer device for the first time, where both ZnO and Al2O3 are active switching layers exhibiting resistive switching properties. The I-V characteristics of the device initially show bipolar resistive switching (BRS) for a few cycles (∼12) before permanently switching to CRS with the extension of SET voltage. The stable CRS state of the device exhibits a high current of ∼500 μA during the ON-state and low current of 3 × 10−7 A during OFF-state at low input voltages (−0.5 V to 0.5 V) enables the proposed device suitable to use in crossbar array to mitigate the sneak path current. The device performance to write and read processes is evaluated with pulses of magnitudes ∼|2.5| V and 1.3 V, respectively, and showed a ∼60 μA difference in read-out current between data bits 0 and 1. Similarly, the device's power consumption is also measured to elucidate that the device is suitable to use as a memory unit with power consumption in the order of microwatts (μW). Further, the possible switching mechanism is demonstrated based on oxygen vacancies migration.

enables the proposed device suitable to use in crossbar array to mitigate the sneak path current. The device performance to write and read processes is evaluated with pulses of magnitudes ∼|2.5| V and 1.3 V, respectively, and showed a ∼60 µA difference in read-out current between data bits 0 and 1. Similarly, the device's power consumption is also measured to elucidate that the device is suitable to use as a memory unit with power consumption in the order of microwatts (µW). Further, the possible switching mechanism is demonstrated based on oxygen vacancies migration.

I. INTRODUCTION
C OMPLEMENTARY resistive switching (CRS) devices were first proposed in [1] to use in large crossbar arrays (CBA) to mitigate the sneak path current problem. In addition, recently, they are receiving attention in the field of neuromorphic computing [2] and logic applications [3]. The sneak path current is the leakage current originating from multiple low resistance paths offered by unselected cells in the crossbar memory arrays [4], [5], [6], [7], [8]. Sneak current mitigation in CRS is achieved by the high resistance offered by CRS devices during the low voltage regimes, also by the option of encoding the data to different high resistance states (HRS), namely HRS/LRS and LRS/HRS. Generally, CRS devices are developed with the anti-serial configuration of bipolar resistive random-access memory devices (RRAM) [9]. For example, Manuscript [5], [10], [11], [12], [13] can be used to develop CRS devices when following the anti-serial configuration. Instead, several single stacked RRAM devices such as HfO x [14], Cu 2 O [15], and bilayer devices such as Ta 2 O 5 /Ta, , [5], [11] also exhibit CRS characteristics. Even though several ZnO, Al 2 O 3 and their bilayer structures have been reported in literature [16], [17], [18], [19], [20], none of them show complementary resistive switching characteristics. Hence in this work, the CRS behavior of Au/ZnO(10 nm)/Al 2 O 3 (10 nm)/Fluorine doped tin oxide (FTO) device has been reported for the first time. The paper focuses on the fabrication, characterization, performance of the device as memory, in addition to describing the possible mechanism of CRS characteristics of Au/ZnO(10 nm)/ Al 2 O 3 (10 nm)/Fluorine doped tin oxide (FTO) device. In the proposed device, ZnO and Al 2 O 3 are the active resistive switching layers formed with the atomic layer deposition (ALD) method. Even though the I-V characteristics of the device initially exhibited bipolar resistive switching (BRS) behavior, it has shown momentary transition to stable CRS after a few cycles. The ON-state current measured for the device during CRS is ∼500 µA, and the OFF-state current is found to be very low as 30 µA. In addition, as expected, the device has shown high resistance at low voltage regime of −0.5 V to 0.5 V, ensuring high nonlinearity while selecting the read/write biases of selected/unselected devices in the CBA. Hence the presented CRS device is suitable to mitigate the sneak path current in a CBA. Moreover, the device responded well to read/ write process and has a good window of read margin (∼1.8 V). In addition, the device also shows microwatt power dissipation during read/ write process that enables the device to use in medium power applications.

II. EXPERIMENT PROCEDURE
Initially, the Fluorinated Tin Oxide (FTO) coated glass is sonicated and prepared to use as the bottom electrode (BE) [4]. Further, the active layers are formed with atomic layer deposition (ALD). For the entire deposition process, the temperature of the top chamber of ALD is set at 110°C and pressure is maintained below 0.4 mbar. Under this ambiance, the active switching layers; ZnO and Al 2 O 3, were deposited by controlling the purge gas (N 2 ) exposure time with the controlled flow of precursors (TMA, Diethyl Zinc) and oxidizer (water). The bottom chamber temperature is set to 200°C for Al 2 O 3 and 150°C for ZnO 1536-125X © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information. Further, the structural characterization is performed using Ellipsometer, FEI Quanta 400F FESEM with EDX, and Electrical characterization is performed with an Agilent B2912A precision source measure unit by keeping the sample in the dark chamber at room temperature.
In the next section, the structural and electrical characterization of the device, including the I-V characteristics and the response of the device to pulse input, is described. Further, various parameters, and reliability measures, are discussed. Then, the optimization of the device with different thicknesses of active switching layers is also presented. Finally, a theoretical study on the possible switching mechanism and conduction mechanism of the proposed bilayer device is discussed.

III. RESULTS AND DISCUSSIONS
FESEM analysis has been carried out in samples after electroforming and subsequent cycles. It has been observed from the structural analysis is that the material deposition is uniform, as shown in Fig. 2(a), depicting the Gold deposited device area. Fig. 2(b) depicts a cross-section of the device that illustrates the existence of layers obtained with SEM at 1µm scale magnification. Interestingly, defect/damage is observed on the surface of randomly selected samples, as shown in Fig. 2(c), indicating that the formation might have occurred in this area. Then, the elemental distribution at that area is performed with EDX to found that the top electrode is damaged/defected (not shown). The intermediate layers also showed distinguished areas revealing the presence of reactions at the entire structure, backing up the theory of the possible formation of conduction filament (CF), which is in line with [21]. Fig. 2(d) shows the distribution of oxygen at the active layers reflecting the defect pattern. From FESEM analysis, it can be interpreted that reactions are happening on both top and bottom interfaces to substantiate the filament formation in CRS.
Electroforming (EF) is the initial step to carry out in most of the RRAM devices. In some CRS-based devices, the forming process has a significant role in defining the device characteristics [14], [22]. In contrast, the forming step has no relevance [23], [24] in some other devices. In the proposed device, the electroforming has been carried out at both positive and negative polarity of input voltage with a low compliance current. However, it has been observed that forming with negative voltage showed high variability in its I-V characteristics with insignificant Roff/Ron ratio due to uneven distribution of excessive defects present in the device, whereas EF with the positive voltage provided consistent characteristics [25]; therefore, this work focuses on positively formed devices and their characteristics.
In the proposed device, the EF is performed by applying a voltage sweep of 0 to 8 V at a compliance current of 100 nA. After EF, various SET/ RESET cycles are followed. The device exhibited BRS behavior in response to initial cycles; then, it underwent a momentary transition before permanently changing to CRS characteristics. The BRS characteristics are shown in Fig. 3(a), which occurred at a compliance current of 5 mA with continuous input sweep from −2.5 V to 3 V at stepping voltage of 0.01 V, that results in an average value of SET and RESET voltages, −1.73 V and 1.5 V respectively. In addition, the maximum device current in BRS is limited by the self-compliance feature of the device, which is measured as 500 µA. In Fig. 3(a), the low resistance state (LRS) of BRS characteristics is indicated as LRS1, and the high resistance state (HRS) is marked as HRS1. However, after a few cycles (∼12), the device showed a transition from BRS behavior as in Fig. 3(b), where the SET current of the intermediate stage is increased beyond the SET current achieved with BRS (LRS1), marked as early-SET in Fig. 3(b) and this new low resistance state is marked as LRS2. Then, the device started exhibiting CRS behavior as plotted in Fig. 3(c), which is the stable characteristic of the device since the device never drives back to the initial BRS as the state transition at the low resistance from LRS1 to LRS2 has made a permanent change in the device.
The transition from BRS to CRS characteristics is reported in several devices. A few devices exhibit the transition while modulating the SET compliance current [9], whereas others show transition while extending the input SET sweep voltage [5], [26]. In our study, a steady compliance current (Ic) is applied to the device throughout the characterization and the transition is observed while extending the input sweep voltage from −2.5 to −2.8 V with variation in stepping voltage from 0.011 V to 0.0116 V. This transition from BRS to CRS characteristics is owing to the change in characteristics of the conduction filament (CF) [9], [27], [28].
The CRS characteristics given in Fig. 3(c) can be analyzed with four threshold voltages; Vth1, Vth2, Vth3, and Vth4. At threshold voltages Vth1 and Vth3, the device enters to completely ON-state with both active layers switch into LRS state, whereas during Vth2 and Vth4, the device transit to one of the two high resistance states, i.e., state-0 (LRS/HRS) or state-1  (HRS/LRS). In CRS devices, the data is stored in one of the high resistance states with read voltage defined between a range of voltages limited by the threshold voltages |Vth1-Vth2| or |Vth2-Vth3|. However, the destructive read causes a major hindrance in the device usage [29] though there are several methods to choose the read voltage to avoid the destructive read [30]. The read-window in the proposed device is ∼1.8 V. From multiple cycles of BRS and CRS as shown in insets of Fig. 3(a) and (c), it has been noticed that a shift is occurred in the SET and RESET voltages of the device when its characteristics permanently changed from BRS to CRS. The statistical distribution of this voltage shift is performed using the Weibull distribution as plotted in Fig. 3(d), where CRS SET means the SET process occurs at a threshold voltage Vth3 and CRS RESET means the RESET occurs with threshold Vth2. Even though the device exhibits self-compliance, the device characteristics obtained with different current compliance is given in Fig. 4(a). In Fig. 4(a), the device current at LRS and HRS increases with an increase in compliance current, which can be described as the change in the properties of the conduction filament such as diameter or number of oxygen vacancies with increased compliance current. Similarly, an analysis based on the stop voltage is also carried out as given in Fig. 4(b), where at a Vstop of −2.7 V, the device switched to SET state as part of BRS. As the stop voltage extended further, the device showed both SET as well as RESET switching as part of CRS. It has been noticed that the initial resistance of the device at low voltage (from 0 to −1.5 V) is slightly decreasing with an increase in stop voltage. However, the LRS shows variations irrespective of the stop voltages. Fig. 4(c) plots the mean and error in the measured current value at various voltages during multiple cycles, revealing that current is distinguishable beyond 1.5 V irrespective of the polarity.

A. Performing Read and Write With Pulse Input
The results of read/write and power are obtained from the Keysight source measurement unit (Agilent B2912A), where  the pre-generated (MATLAB) input pulse train of the write-read pattern is fed as the input source. The corresponding result is measured as given in Fig. 5, where the RESET transition occurs from 2 V to 3 V during the positive polarity and ∼ −2.4 V to −3.8 V during the negative polarity of the input. Therefore, based on the write scheme given in [31], the write voltage is selected from within the above-given ranges. The write voltages chosen for the particular device are −2.5 V, 2.1 V, and read voltage is specified as ∼1.3 V, falling near the subthreshold region. Further, to demonstrate the write/read processes, the device is subjected to several read/write pulses. Among them, three consecutive cycles of write, read are shown in Fig. 5, where alternate cycles run to perform write-1, read-1, followed by write-0, and read-0. The multiple read scenario has not been considered in this study. From Fig. 5, we observed that the read current obtained while reading data bit 1 and 0 are distinguishable with ∼ 60 µA difference in read-out current.
Similarly, write-1 and write-0 show the current values 300 µA and 200 µA, respectively. Thus, the device is operating under low magnitudes of write voltage (< |3| V), and current (in µA) enables it to use in medium power (µW) memory applications. The power dissipation (PD) across the device on response to sweep of the sawtooth waveform (not shown) reveals that PD is zero at lower voltages, describing the possibility of sneak path current reduction. Moreover, the PD measured in response to pulse input while writing is ∼450 µA, as depicted in Fig. 6. Similarly, reading the data bits' 1' and '0' require a PD of 130 and 65 µW, respectively, as shown in Fig. 6. However, as expected, the power dissipation during the read process is comparatively lower than that of data write, which signifies the use of the device in medium power memory applications.
Owing to the stable CRS behavior exhibited on response to pulse and DC inputs, the device can be used in CBA to mitigate sneak path current after its low off current of ∼3 × 10 −7 A present at low input voltage ≤|0.5| V, which effectively blocks the possible leakage current originating from the memory array. Therefore, when connecting the device in a crossbar array, read bias voltage (Vread/2) applied to unselected cells in the array can be ≤|0.5| V, read margin applied to the selected cell (Vread) can be in the range of ∼1.0 V to 1.8 V.
Next, the switching time and reliability of the device are given in Figs. 7 and 8, respectively. In Fig. 7(a), the device shows SET and RESET switching at both positive and negative polarities of DC sweep voltage. The SET process at negative polarity is abrupt, occurring at 20 µs, whereas the SET switching at positive bias is gradual and happens at 0.30 ms as marked in Fig. 7(a). However, the device shows microseconds switching time when performing read and write with input pulses. While reading, the read current increases to a maximum value at 5 µs of the  read pulse as given in Fig. 7(b), whereas writing to the device responds in 8 µs as given in Fig. 7(c). Fig. 8(a) shows the device's endurance for multiple cycles, and Fig. 8(b) demonstrates the device retention capability when performing read at ∼1.3 V. In our experiment we tested the endurance up to a few cycles only, but we found that the device maintains the levels if we extrapolate further. Generally, the endurance can be improved by precise control on process, environmental parameters such as the temperature, pressure, and control on the amount of oxidizing agent. In addition, inserting an additional tunneling layer may reduce overshoot during SET process, which may also improve endurance characteristics. Moreover, from the literature, we could find that controlling the stress time and the using a triangular pulse instead of a square pulse may also help to enhance the endurance cycles. [32], [33].

B. Optimization With Active Layer Thickness
With a focus to optimize the device performance, three different sets of samples with different active layer thicknesses are tested, as shown in Fig. 9(a), (b), and (c). While comparing, it could be observed that the off current in devices with 10 nm active layer is higher than that of the devices with 30 and 40 nm thickness. Moreover, leakage current is found to be decreasing with an increase in active layer thickness. Likewise, the devices with thicker oxide show a better OFF (HRS/LRS or LRS/HRS) to ON (LRS/LRS) ratio. The following section describes the theoretical approach to the possible Mechanism of CRS switching and current conduction in the bilayer device.

C. Possible Mechanism of Forming and Switching
Generally, the switching process in RRAM devices can be explained based on the formation of conduction filament. Two significant mechanisms associated with filament formation are; valance change memory (VCM) [34] and electrochemical metallization memory (ECM) based switching. As the electrodes used in the proposed device are inert (Au and FTO) [35], [36], [37], and the active layers are well-known oxides switching with oxygen vacancies, the possibility of ECM-based switching is ruled out. Also, in our study, the influence of protons or moisture on switching is not considered [38]. From various experiments conducted, it has been interpreted that the filament formation in the proposed device is based on oxygen vacancies. Therefore, the device is likely to be falling under the category of VCM [39]. In our analysis with single-layer devices, we have observed that the ZnO layer is more conductive due to excessive defects, which might degrade device performance [36]. Hence, the as-deposited device had been subjected to EF with a positive sweep, limiting the number of defects in the layer. The possible mechanism can be explained as the migration of positively charged defects to bottom of ZnO layer, leaving a depletion layer at the top interface. However, further increase in voltage causes the presence of maximum electric field at that region, which results in the formation of oxygen ions.
That may further limit the number of oxygen vacancies in the ZnO layer to form a uniform/constant distribution of oxygen vacancies in the device [25]. Subsequent initial SET/RESET cycling at higher compliance current results in the formation and rupture of filament at the ZnO layer. That too can be obtained with the negative and positive polarity of the input voltage, respectively. In this case, rupture of conduction filament occurs when performing the RESET switching at a higher external compliance current, and the possible mechanism is associated with Joule heating [25], [34].
Further, the transition from BRS to CRS occurs due to the second electroforming process at the Al 2 O 3 layer with the modulation of input voltage at a higher compliance current [34]. In this study, the mechanism of CRS in ZnO/ Al 2 O 3 bilayer structure is explained with the concept of redistribution [5], [24] of oxygen vacancies within ZnO and Al 2 O 3 layers.
The switching process that occurs at CRS is explained in Fig. 10, where at input voltages <−0.8 V, the device is at HRS with filament free ZnO layer and presence of oxygen vacancy filament at Al 2 O 3 (LRS) layer. Thus, the resistance state of the device becomes HRS/LRS or state-1, as indicated in Fig. 10(a). Then, as the input sweep reaches −0.8 V, the oxygen vacancies migrate toward the top electrode to form filament in the ZnO layer [37]; thereby, the device enters an LRS/LRS state or completely ON-state shown in Fig. 10(b). On further increase in voltage beyond −2.4 V causes more oxygen vacancies to migrate towards the top electrode resulting in the rupture of filament from the bottom electrode interface; as a result, the lower Al 2 O 3 layer becomes depleted, as shown in Fig. 10(c), consequently the device state changes to LRS/HRS state or state-0 [35].
Next, a sweepback of the input signal causes the device to remain in the current state-0 until the applied input voltage reaches ∼1.2 V of the positive cycle. Subsequently, when a positive input voltage of 1.2 V is applied to the top electrode, an electric field is set up across the device, though most of the field appears across depleted resistive Al 2 O 3 layer and concentrated electric field appears at tip of the conduction filament than at the top flat interface [40].
As a result, instead of rupturing the conduction filament from the top electrode interface, oxygen vacancies present at ZnO/ Al 2 O 3 interface drift towards the bottom electrode and eventually forms a filament spanning across Al 2 O 3 and ZnO layer as demonstrated with Fig. 10(d), where the arrows show the dominance of the electric field at bottom electrode interface than at the top interface and the corresponding state becomes LRS/LRS. Further increase in positive voltage causes Oxygen vacancies to get detached from the top electrode, and upper part of the filament breaks to attain HRS/LRS state as shown in Fig. 10(e), eventually to reach final stage shown in Fig. 10(f), which is same as initial state given in Fig. 10(a). The mechanism illustrated in Fig. 10 correlates with the device's resistance developed as shown in Fig. 11, described with six points a, b, c, d, e, and f. In Fig. 11, the initial state of the device achieved with the negative polarity of input voltage is HRS/LRS or state-0 (marked as 'a' in Fig. 11) with the resistance value ∼32 KΩ, as the magnitude of input voltage increases further, the device switch to ON-state (as marked as b in Fig. 11) with its resistance as low as 10 KΩ. Subsequently, when the input sweep reaches −2.4 V forces the device to switch to a higher resistance state of approximately 42 KΩ, i.e., state-1 (marked as c in Fig. 11). During the positive voltage sweep, the current through the filament increases and finally settles at a resistance of approximately 32 KΩ as marked with f in Fig. 11 after going through completely ON-state (marked as d, e in Fig. 11). From the figure, it is noteworthy that the resistance at points a (state-0) and c (state-1) are distinguishable with an approximate difference between them is 10 KΩ which indicates that the HRS arise due to the rupture of filament in ZnO and Al 2 O 3 layers respectively as indicated in Fig. 10(a) and (c).
As discussed in section B, CRS devices with different thicknesses of ZnO and Al 2 O 3 layers showed different resistance values at low voltages due to the high series resistance provided by the ZnO or Al 2 O 3 layer with large thicknesses compared to the device under test (DUT). It has been observed that, as the total thickness of the active layers (ZnO/Al 2 O 3 ) increases, the leakage current decreases due to the reduction in tunneling/leakage current through the device (owing to considerable tunneling distance due to large device thickness), which in turn affects the resistance of the device. Thus, it also affects the OFF state (HRS/LRS or LRS/HRS) to ON state (LRS/LRS) ratio. The OFF resistance obtained for the active layers with thickness 40, 30, and 20 nm is in the ranges of 1E10 Ω, 1E7 Ω, and 4E4, respectively.
Next, the current conduction mechanism associated with the device is illustrated with the help of experimental data and fitting models. As shown in Fig. 12, at HRS (for both positive and negative polarities), the slope obtained between ln(I) and ln(V) illustrates a proportional relationship between I and V 2 . It further demonstrates that the major current conduction mechanism of ZnO/Al 2 O 3 bilayer device is due to trap controlled-space charge limited conduction (TC-SCLC) [41]. Similarly, at LRS (positive polarity), the relationship between ln (I) and V 1/2 depict that the current conduction at Au/ZnO interface is due to Schottky conduction [9], which is also consistent with the conduction mechanism reported for ZnO based switching memories.

IV. CONCLUSION
The complementary resistive switching exhibited by Au/ZnO/Al 2 O 3 /FTO device is explained, and the response of the proposed device to read-write pulses is demonstrated. The device is found to be effective to use in crossbar arrays as its low intrinsic leakage current (3 × 10 −7 A) present at low voltages eliminates the sneak path current, and the overall power dissipation of the device is found to be in microwatts. The reliability of the device is tested for multiple endurance cycles, and the device is optimized with various thicknesses of the ZnO and Al 2 O 3 oxide layers. The possible switching mechanism in the proposed device is explained as the oxygen vacancy-based switching, and SCLC is interpreted as the dominant conduction mechanism.