A High Efficiency Non-Isolated Three-Phase Unfolding Based Electric Vehicle Powertrain

Three-phase unfolding based converters offer a radically different approach to two-stage dc to three-phase ac conversion, with potential benefits for electric vehicle (EV) powertrains. However, current research on non-isolated three-phase unfolding, particularly for EV powertrains, is limited. This paper presents a non-isolated bidirectional buck-boost three-phase unfolding system for EV drivetrains. The proposed converter incorporates a non-inverting buck-boost converter and a voltage balancer circuit in the dc-dc stage. Unlike existing unfolding systems in the literature that require two dc-dc converters capable of handling full system power, the balancer in the proposed system only handles a fraction of the total power, resulting in reduced size and improved efficiency of the converter when compared to a conventional two-stage EV powertrain. The paper provides detailed design guidelines and presents a straightforward control strategy for the proposed converter. To evaluate its performance, a 5 kW prototype is constructed and tested with an induction motor. The experimental results demonstrate peak efficiencies exceeding 98%.

Three-phase unfolding based converters adopt a fundamentally distinct approach to the conversion of dc to three-phase ac in a two-stage system.Unlike traditional methods, these converters exploit the flexibility of the intermediate dc-link voltage, enabling the generation of sinusoidal outputs using only fundamental-frequency switching in the inverter stage.This is achieved by employing two series-connected, varying dc-link voltages at the output of the dc-dc stage, which are subsequently unfolded into three-phase voltages by a three-level inverter [8].This unique configuration virtually eliminates the switching losses in the inverter stage, leading to improved overall efficiency [9] and reduced filtering requirements [7].
A typical three-phase unfolding based dc-ac system is depicted in Fig. 1(a).It comprises a dc-dc stage and an unfolder stage.The unfolder stage necessitates the use of a three-level inverter, such as the neutral point clamped (NPC) converter [7] or a T-type inverter [9], [10].For the dc-dc stage, most existing approaches in the literature use two converters connected in an input-parallel output-series fashion [7], [8], [11].The output-series connection requires that the two converters be isolated.Therefore, bidirectional systems have employed dual active bridge derived topologies like the dual-bridge seriesresonant converter (DBSRC) [7] shown in Fig. 1(b) or asymmetric secondary-modulated converter (ASMC) [8], while unidirectional systems have utilized the phase-shifted full-bridge topology [11].In such cases, each dc-dc converter must be rated to handle a peak power equal to the total active power of the system, resulting in a dc-dc stage peak power rating twice the total active power [12].
In [12] and [13], a single isolated converter with a three-level full-bridge on the unfolder stage side is employed in the dc-dc stage to improve efficiency and power density.However, in EV powertrain applications, galvanic isolation is unnecessary, and using an isolation transformer introduces drawbacks in terms of size and efficiency.
Existing non-isolated unfolding approaches have been limited to the Swiss rectifier [14] and its bidirectional variants [9], [10].These converters are tailored for grid-connected applications, offering only boost operation from dc to ac.In the case of EV powertrains, the required motor voltage varies with speed, from very low to the rated voltage.Given that the unfolder stage lacks voltage regulation capabilities, all regulation tasks must be managed by the dc-dc stage, necessitating its ability to provide buck operation or buck-boost operation, in case a higher maximum dc-link voltage is desired.Buck-boost dc-dc stages have been used in EV charging [15] as well as powertrain applications [16], with [16] utilizing conventional high switching frequency VSI stage.
This paper presents a non-isolated bidirectional buck-boost three-phase unfolding based dc-ac converter for EV powertrain applications [1].The proposed configuration incorporates a noninverting buck-boost (NIBB) converter and a voltage balancer circuit in the dc-dc stage and does not require transformer isolation to generate the series connected varying dc-links.Key contributions include: (1) in-depth analysis of the circuit's operation, particularly the power processed by the NIBB and the balancer, (2) analytical expressions for semiconductor stress and passive component design, including inductor value selection for achieving zero-voltage switching in the high-frequency dc-dc stage, (3) comparison between the calculated efficiencies of the proposed system and the conventional powertrain comprising a boost converter and a VSI, (4) a voltage-based control strategy supported by simulation results, and (5) experimental validation using a 5 kW hardware implementing sensorless field-oriented control on an induction machine, achieving a peak efficiency of 98.4%.

A. Three-Phase Unfolding Principle
Assume that the desired three-phase balanced sinusoidal lineline voltages are defined by (1).
where V m is the peak voltage and ω = 2πf ac is the angular frequency.The waveforms of the system are divided into six equal sectors per fundamental cycle, as depicted in Fig. 2. The dc-dc stage of the unfolder system produces two seriesconnected varying dc-link voltages v xy and v yz .Both these voltages are piecewise sinusoidal, varying between zero and √ 3V m /2 at 3f ac .Table I provides the relationship between the dc-link voltages and the ac line-to-line voltages in different sectors.The dynamic dc-link voltages create a soft dc-link, allowing the use of small filter capacitances to address the switching ripple without requiring bulk capacitance.Fig. 2. Waveforms of the existing three-phase unfolding based system depicted in Fig. 1, showing (a) three-phase ac line-line voltages, (b) dc-link voltages, (c) three-phase ac line currents, (d)-(f) dc-link currents, and (g) powers processed by the two dc-dc converters for a power factor of 0.9.

TABLE I DC-LINK AND AC WAVEFORM RELATIONSHIPS
The dc-dc stage utilizes high-frequency PWM to produce v xy and v yz , which form portions of the required three-phase sinusoidal voltages as shown in Fig. 2(b).The sum of these two voltages v xz is also piecewise sinusoidal, with a six-pulse waveform per fundamental cycle.The unfolder stage makes use of a three-level inverter, such as the T-type inverter, to unfold the dc-link voltages into the three-phase sinusoidal voltages of (1) using fundamental frequency switching.The three-level inverter allows connection of each phase output to the top, middle, or bottom dc-link terminals.Thus, in each sector, it is possible to apply v xy , v yz , v xz , or their negations between two phases.This is depicted in the equivalent circuits of Fig. 3  showing unfolder operation using a T-type inverter for sectors 1 and 2, respectively.For instance, for the duration of sector 1, the T-type inverter is switched in a manner such that v yz is applied as v ab , −v xz as v bc , and v xy as v ca .The unfolder stage unfolds voltages from the dc-dc stage without modulation capability, leaving control and regulation tasks exclusively to the dc-dc stage.
The operation of the unfolder stage results in the reflection of three-phase line currents, as defined by (2), into corresponding dc-link currents i x , i y , and i z .Fig. 2(c) illustrates the ac line currents while Fig. 2(d)-(f) show the resultant dc-link currents for a power factor of 0.9.Table I gives the relation between dc-link currents and the ac line currents in different sectors, independent of power factor.
where I m is the peak of the line currents and φ is the power factor angle.

B. Existing Unfolder Systems
Existing literature commonly utilizes a dc-dc stage configuration with two converters in an input-parallel output-series arrangement, as shown in Fig. 1(a).Consequently, these two converters handle the instantaneous powers p 1 and p 2 : The power factor dependency of the waveforms of i x and i z results in a corresponding influence on the power processed by the two converters.In the case of EV motors, such as PMSMs and induction motors, the power factor typically ranges from 0.85 to 0.95 at the rated power level [17].Within the power factor range of 0.8 to 1, the power processed by each converter varies between zero and the full active power P out handled by the entire unfolder system.For instance, Fig. 2(e) illustrates the power processed by the two dc-dc converters specifically for a power factor of 0.9.
The significance of power processed by individual converters in the system lies not only in power loss considerations, but importantly in its implications for converter design.Although, on average, each dc-dc converter handles half of the total power,  both converters must be designed to accommodate the full power rating of the system.This requirement results in oversized passive components, reducing the power density of the system.

C. Proposed Unfolder System
Fig. 4 shows the proposed non-isolated bidirectional threephase unfolder based dc-ac converter circuit for powertrain applications.The fundamental frequency switching unfolder stage is implemented using a T-type inverter.In order to produce the varying dc-link voltages v xy and v yz , the dc-dc stage employs a non-inverting buck-boost (NIBB) converter and a partial power processing buck-boost type voltage balancer circuit.The balancer functions as a parallel branch, drawing a fraction of the NIBB output current while the remaining current flows directly to the T-type inverter.
The NIBB converter produces the six-pulse voltage v xz from the constant battery voltage.Since the motor voltage requirement can be greater than or less than the battery voltage, a buckboost topology is used to generate v xz , especially considering 800 V dc-links derived from 400 V batteries [18].
The NIBB offers high efficiency when operated in separate buck and boost modes, where the duty cycles D xz,bk and D xz,bt are given to transistors S 1 and S 4 , respectively.The expressions for the two duties for buck and boost operations are given in Table II.During buck operation, S 4 is kept continuously off while during boost operation, S 1 remains on.
Derived from the inverting buck-boost topology [19], the voltage balancer circuit is utilized to split the six-pulse dc-link voltage v xz into the two series connected dc-link voltages v xy and v yz , essential for unfolding operation.The operation of the balancer can be conceptualized as a buck operation, where v xz serves as the input voltage and v yz as the output.Consequently, the duty ratio of switch S 5 is given in Table II, varying between zero and one within each sector of operation.Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

D. DC-DC Stage Power Processing in the Proposed System
For the proposed converter, the power processed by the NIBB and the voltage balancer can be determined by analyzing the different currents in the dc-dc stage.The various active and passive components of the dc-dc stage will process a high-frequency current component and a low-frequency average component, which varies at either three times or six times the ac fundamental frequency.

1) Power Processed by the Voltage Balancer:
The lowfrequency component of the balancer inductor current īL 2 can be found using the following expression: where īC xy and īC yz are the low-frequency components of the currents through the dc-link capacitances C xy and C yz respectively due to the varying dc-link voltages across them.The power processed by the voltage balancer circuit can therefore be found as where īS 5 is the low-frequency component of the current through switch S 5 .
Eqs. ( 4) and ( 5) reveal a significant dependency of the power processed by the balancer circuit on power factor and the dc-link capacitive currents, which in turn depend on the capacitance values and the voltage level.At unity power factor, if the capacitances are considered negligible, the balancer handles a peak power equal to half of the total output power.For a power factor of 0.9, and considering the dc-link capacitance values as designed in Section IV, the balancer processes a peak power approximately equal to 60% of the full output power.
2) Power Processed by the NIBB: The NIBB converter inductor current waveform depends on whether the converter operates in buck mode or boost mode.For buck mode operation, since switch S 3 is always on, the low-frequency component of the NIBB inductor current īL 1 ,bk is given by However, the maximum power processed by the NIBB will be during boost operation.For boost mode operation, the lowfrequency component of the NIBB inductor current īL 1 ,bt is given by Hence, the maximum power processed by the NIBB converter will be determined by the following expression: The power processed by the NIBB converter remains nearly constant, equal to the full output power, with slight variations around P out due to the low-frequency capacitive currents.In Fig. 5(d) and (e), the waveforms of the balancer and NIBB inductor currents during boost operation are illustrated, based on the specifications and component values in Table III, considering a power factor of 0.9.Fig. 5(f) depicts the corresponding powers processed by the NIBB and the voltage balancer circuits.

III. SYSTEM CONTROL
In the three-phase unfolding system, the unfolder stage operates as an advanced switch that interconnects the dc-link voltages produced by the dc-dc stage to form three-phase ac voltages.Its primary role does not involve voltage or current regulation, which is handled by the dc-dc stage.Fig. 6 showcases a block diagram presenting a voltage-based control scheme for the proposed three-phase unfolding based EV powertrain.The system controller can be divided into three sections: the unfolder stage switching scheme, reference generation for the dc-dc stage, and dc-dc stage control.Within this framework, the EV motor speed control strategy provides the necessary machine terminal phase voltage references (v * a , v * b , v * c ), which are then generated by the powertrain following Fig. 6.

A. Unfolder Switching
Although the amplitude of the output remains unchanged during the switching of the unfolder stage, it is crucial to synchronize the unfolder stage switching with the output of the dc-dc stage.The switching signals applied to the unfolder stage are fixed within each sector of operation, regardless of the amplitude of the dc-link voltage or the desired output.The determination of the sector is based on the machine terminal voltage references, as shown in Fig. 7(a).Each sector corresponds to a specific configuration of maximum and minimum phase voltages.For instance, during sector 1, v * c is the maximum phase voltage, and v * b is the minimum.Once the sector is identified, the necessary switching signals for the T-type inverter devices are provided using the switching scheme depicted in Fig. 9(c).

B. Reference Generation for DC-DC Stage
In order to generate v * a , v * b , and v * c at the converter output, corresponding dc-link voltages must be produced by the dc-dc stage.Given the phase voltage references, the dc-link voltage references can be determined by first identifying the maximum, median, and minimum voltages among the phase voltages.Thereafter, the dc-link voltage references are determined using (10).The dc-link reference generation is illustrated in Fig. 7.

C. DC-DC Control
The controller design for the dc-dc stage follows the conventional approach of utilizing small-signal converter models obtained through state-space averaging.As the NIBB converter operates in separate buck and boost modes, each mode possesses a distinct control-to-output voltage transfer function.To accommodate both modes, a unified controller G C1 (s) is designed to provide the necessary compensation.
Switching signals for the NIBB buck and boost devices are generated using two references and one carrier.From the controller output v C1 , two references v C,bk = v C1 and v C,bt = v C1 − V P W M are generated for buck and boost devices respectively, where V P W M is the amplitude of the single carrier.
As mentioned earlier, the voltage balancer functions as a buck circuit where v xz serves as the input and v yz as the output.The small-signal modeling and controller design for the balancer are carried out using the same approach.Consequently, two PI controllers are designed for the dc-dc stage: G C1 (s) for the NIBB buck and boost modes, and G C2 (s) for the balancer circuit.
In order to improve the controller response and minimize any steady-state errors, the NIBB and balancer duties defined in Table II are given as feed-forward to the controller output as shown in Fig. 6.Simulation results presented in Fig. 8 showcase the impact of the feed-forward duty.The feed-forward mechanism notably enhances the reference tracking performance of the controller, particularly at sector boundaries, as illustrated in Fig. 8(a) and (c).The total harmonic distortion (THD) of the line voltages improves from 3.18% in Fig. 8(b) to 0.3% in Fig. 8(d).

A. Semiconductor Stress
The voltage and current waveforms, as well as the switching signals, for leg a transistors of the T-type converter are illustrated Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.  in Fig. 9.The devices Q 3a and Q 4a operate in a complementary switching manner to Q 1a and Q 2a respectively.The waveforms and switching signals for legs b and c are similar, with a phase lag of 2π/3 and 4π/3 radians respectively.Besides fundamental frequency switching, all devices of the T-type inverter switch at zero voltage for all power levels and power factors.
The peak voltage stress on Q 1j and Q 4j is V m , while Q 2j and Q 3j experience a peak stress of √ 3V m /2, where j can be any of the phases a, b, or c.The root mean square (rms) values of the currents through the T-type switches can be calculated from Fig. 9.The rms current stress on Q 1j and Q 4j is given by (11), and that on Q 2j and Q 3j is given by (12).
In the dc-dc stage, the balancer devices (S 5 and S 6 ) and the boost devices of the NIBB (S 3 and S 4 ) are stressed to a peak voltage of V m , while the buck devices of the NIBB (S 1 and S 2 ) are stressed to v dc .
The low-frequency components of the balancer and NIBB inductor currents are given by ( 4), (6), and (7).In addition to the varying low-frequency average, these inductor currents also exhibit high-frequency ripple, the peak-to-peak value of which varies over each sector.The varying peak-to-peak ripples of the balancer inductor current, the NIBB inductor current during buck operation and the NIBB inductor current during boost operation are given by ( 13)- (15), respectively.
The rms current of the transistor devices in the dc-dc stage for the kth high-frequency cycle can be calculated using where D M,k is the duty of that switch for the kth cycle, and īL,k and Δi L,k are the low-frequency component and the peakto-peak ripple of the corresponding inductor current for the kth cycle.The overall rms current over a low-frequency cycle can then be found by summing the contributions from each highfrequency cycle.

B. Passive Component Design
The inductance values of the dc-dc stage are selected so as to enable zero-voltage switching quasi-square wave (ZVS-QSW) operation over a majority of the converter power range.In the ZVS-QSW approach, the inductor current peak-to-peak ripple is kept large enough such that the inductor current becomes sufficiently negative at the turn-on of the main switch leading to turn-on at zero-voltage [20].
The EV motor drive operates at a wide range of voltage and power levels, leading to wide variation in ripple amplitudes and average inductor current values.Seeking to maximize the ZVS region while maintaining a constant switching frequency, the NIBB inductance value is selected to allow ZVS-QSW operation at the full converter rating which occurs during boost operation.Hence, from (15) with Δi L 1,bt > 2I dc,max , where P out,max and V m,max are the full converter rating and maximum peak line-to-line voltage respectively.The varying duty ratio of the voltage balancer within each sector causes an inductor current ripple that goes to zero at the sector boundaries.Consequently, it is not possible to achieve continuous ZVS operation for both the balancer transistors throughout the entire sector duration.Therefore, the balancer inductance value is kept low enough to facilitate ZVS operation for a significant duration within the sector.
The rms currents of the inductors are determined using a similar approach to that of the device rms currents.The inductor rms current for the kth high-frequency cycle is calculated as follows: Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

TABLE IV CALCULATED AND SIMULATED VALUES OF RMS CURRENTS
where īL,k and Δi L,k are the low-frequency component and the peak-to-peak ripple of the corresponding inductor current for the kth cycle.
The dc-link capacitance values are designed based on voltage ripple specifications.The high-frequency balancer inductor current ripple is divided between C xy and C yz , which leads to capacitance values given by where Δv xy,max is the high-frequency ripple specified for v xy and v yz .The high-frequency switching ripple on the dc-link voltage v xz is determined by C xz in parallel with the series combination of C xy and C yz .Given that C xy and C yz are taken as equal and the maximum voltage ripple occurs during boost operation, the value of C xz is decided using (20).
where Δv xz,max is the high-frequency ripple specified for v xz .The dc-link capacitances must balance between restricting the high-frequency voltage ripple and allowing the low-frequency voltage variations that are necessary for unfolder operation [21].
Based on the above design guidelines and the system specifications provided in Table III, the converter's passive components are designed, and the corresponding selected values are presented in Table III.Meanwhile, Table IV provides the rms current values for the switches and inductors of the dc-dc stage under rated conditions.These values are determined using the analytical expressions developed in this section and validated against MATLAB Simulink simulation results, showcasing the accuracy of the analytical approach.
V. EFFICIENCY COMPARISON Table V lists the components selected based on the designed values outlined in Table III.The efficiency advantages of the proposed powertrain are underscored by comparing the calculated efficiency of the proposed system with that of a conventional two-stage PWM powertrain, comprising a boost converter followed by a three-phase VSI as shown in Fig. 10.For the purposes of efficiency comparison, the same components listed in Table V are used for the conventional system of Fig. 10.The boost inductor is taken to be same as the NIBB inductor, and the 1200 V SiC devices from Table V are used for the boost half-bridge.The 900 V SiC switches of the T-type inverter are used in the VSI of the conventional system.The dc-dc  stages of both the conventional system and the proposed system operate at 100 kHz, in line with the high-switching frequencies of recent designs for EV converters [22], [23].Following the current U.S. Department of Energy (DOE) guidelines [24], the comparison is presented for VSI switching frequencies of 30 kHz and 50 kHz, aiming to attain good harmonic performance and control bandwidth [25].
The power loss of various components is estimated following [26].Semiconductor losses are determined in an iterative fashion based on datasheet curves of switching energies and drain-source on-resistance.The ZVS condition of the inductor current is taken into account for switching loss calculations of both the proposed system as well as the conventional system.The inductor loss includes the winding loss and the core loss computed based on the improved Generalised Steinmetz Equation (iGSE) [27].For the dc-dc stage of the proposed converter, average power loss is calculated by determining component energy loss per high-frequency cycle, aggregating over a period, and dividing by the total time.Since the unfolder stage switches at the fundamental frequency and zero voltage, T-type inverter semiconductor switching losses are excluded.T-type conduction losses are computed using (11) and (12).Fig. 11.Calculated efficiencies for 50 Hz, 415 V rms ac output of the proposed unfolder system (Fig. 4) at a dc-dc stage switching frequency of 100 kHz and the conventional boost + VSI powertrain (Fig. 10) with the boost converter operating at 100 kHz and the VSI at 30 and 50 kHz.The calculated efficiency curves for 50 Hz, 415 V rms from a 350 V dc input are shown in Fig. 11 for different power levels.The NIBB and the boost converter exhibit nearly identical losses.The losses of the NIBB are slightly higher due to additional conduction losses incurred in S 1 .The VSI, however, with its six high-frequency switching transistors, incurs significantly higher losses compared to the combined losses of the balancer and the fundamental frequency switching T-type inverter, even at the lower VSI switching frequency of 30 kHz.The balancer operates with just two high-frequency switches and an inductor, whereas the T-type inverter experiences conduction losses for only four devices at any given time.

VI. EXPERIMENTAL RESULTS
A 5 kW experimental prototype of the proposed unfolder system was developed and tested with a three-phase 415 V, 50 Hz squirrel cage induction motor.The prototype, as depicted in Fig. 12(a), employs all-SiC devices, dc-link film capacitors, and ferrite core dc-dc stage inductors.The hardware setup details can be found in Table V. Fig. 12(b) provides a breakdown of the individual weights of the various components of the prototype, achieving a gravimetric power density of 2.66 kW/kg.
To replicate an EV environment and assess the performance of the proposed converter in the laboratory, a simplified vehicle model was devised.The model involved coupling the induction motor to a separately excited dc generator, with the generator's output terminals connected to a controlled power supply and a parallel resistive load.The controlled power supply was configured to draw a constant current, emulating a load unaffected by motor speed, while the resistive load emulated a speeddependent load behavior.As the speed of the motor-generator setup increased, the dc generator's terminal voltage also rose, leading to greater current demand from the resistive load and thus an increased load torque.The specific values for the constant current drawn by the controlled supply and the resistance of the load were carefully chosen to ensure that the induction motor operated at its full rated capacity when at the rated speed, while the speed-independent load consistently maintained a load level equivalent to 20% of the rated load [17].
Fig. 14(a) illustrates the experimental waveforms of the proposed converter, where the motor speed followed the medium phase of Class 3 Worldwide Harmonized Light Vehicles Test Cycle (WLTC), simulating a typical drive cycle in suburban scenarios for high-power vehicles.The drive cycle speeds were scaled to ensure that the maximum speed encountered during the cycle corresponded to the rated motor speed.Speed-sensorless field-oriented control based on model-reference adaptive system (MRAS) estimator was used to control the motor, generating motor phase voltage references that were employed to regulate the unfolding system according to the control diagram shown in Fig. 6.The waveforms in Fig. 14  Similarly, Fig. 14(e) and (f) show the ac and dc-link waveforms respectively during region 2 of the drive cycle.In this region, the motor operates at its rated speed of 1500 rpm (around 50 Hz ac), with the load torque set to its rated value of 25 Nm.The THD of the line-to-line voltage, shown in Fig. 14(e), is remarkably low at 1.3%.To achieve the required performance, the NIBB operates in boost mode, producing a peak line-to-line voltage of 530 V. Additionally, Fig. 14(f) provides a zoomedin view of the dc-dc stage inductor currents.Even at rated power, the inductor current ripple remains sufficiently high to enable ZVS-QSW operation for the NIBB and the balancer switches.
Fig. 15(a) and (b) illustrate the speed tracking performance of the proposed powertrain in response to a step and ramp change in speed, respectively.The plots depict the ac line-line voltage v ab , ac line current i a , speed reference N * r , and the estimated rotor speed in rpm N r,est .In Fig. 15(a), the speed increases from 600 rpm to 1200 rpm under no load, with the stator current limited to a peak of 15 A (for short term overload).In Fig. 15(b), the rotor speed transitions from 600 rpm to 1200 rpm over a duration of two seconds.
The power conversion efficiency of the experimental prototype was measured using a four-channel Hioki PW6001 power analyzer by measuring the input voltage and current with one channel and the three-phase power at the output of the converter using the rest of the three channels.The input dc and output ac currents were measured using a high precision ac/dc current probe CT6843 A. The measured efficiency over the entire speedtorque range of the induction motor used in the experimentation is given in Fig. 13(a).For most regions of the speed-torque graph, the converter efficiency remains more than 97%.Given the 350 V input and the 415 V rated motor, the NIBB operates in buck mode up to a speed of 900 rpm beyond which the NIBB operates in boost mode.The peak efficiencies measured in buck and boost modes are 98.3% and 98.4% respectively, at points A and B shown in Fig. 13(a).Fig. 13(b) depicts calculated loss breakdown at these two points, showing conduction (P cond ), switching (P sw ) and inductor core (P fe ) losses.Unlike point B, at point A the NIBB inductor current ripple is not large enough to enable to ZVS-QSW operation, leading to higher switching Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
losses.Even at point A, the losses of the T-type inverter are less than 17% of the total losses.
The 5 kW setup serves to confirm the circuit's viability, validate its operation, and substantiate the analysis.Through traditional multi-phase interleaving of the dc-dc stage, the proposed system can be scaled up in the range of 60-125 kW [23], [28].In this extended power range, the proposed system becomes applicable to light-duty HEVs, FCEVs, as well as non-sports category BEVs [24], [29].

VII. CONCLUSION
This paper described a non-isolated three-phase unfolding approach for electric vehicle drivetrains.The proposed configuration utilizes a full power processing non-inverting buck-boost converter to produce a six-pulse varying dc-link voltage which is then split into two piecewise sinusoidal voltages for unfolding operation using a partial power processing voltage balancer circuit.The power processed by the dc-dc stage was analytically described and a control scheme was provided which is able to track the varying voltage references with assistance from feed-forwarded duty ratios.Guidelines for the design of semiconductor devices and passive components are outlined.Compared to conventional two-stage EV powertrains, the proposed system demonstrates higher efficiencies.The operation of the proposed system was validated using a 5 kW prototype driving an induction motor over a suburban drive cycle.Efficiencies over 97% were measured over most of the speed-torque range with a peak measured efficiency of 98.4% during boost operation.

Fig. 1 .
Fig. 1.(a) Block diagram of existing three-phase unfolding based systems with two converters in the dc-dc stage.(b) Isolated dual-bridge series-resonant converter (DBSRC) circuit, two of which are used in the dc-dc stage of [7].
Fig.4shows the proposed non-isolated bidirectional threephase unfolder based dc-ac converter circuit for powertrain applications.The fundamental frequency switching unfolder stage is implemented using a T-type inverter.In order to produce the varying dc-link voltages v xy and v yz , the dc-dc stage employs a non-inverting buck-boost (NIBB) converter and a partial power processing buck-boost type voltage balancer circuit.The balancer functions as a parallel branch, drawing a fraction of the NIBB output current while the remaining current flows directly to the T-type inverter.The NIBB converter produces the six-pulse voltage v xz from the constant battery voltage.Since the motor voltage requirement can be greater than or less than the battery voltage, a buckboost topology is used to generate v xz , especially considering 800 V dc-links derived from 400 V batteries[18].The NIBB offers high efficiency when operated in separate buck and boost modes, where the duty cycles D xz,bk and D xz,bt are given to transistors S 1 and S 4 , respectively.The expressions for the two duties for buck and boost operations are given in TableII.During buck operation, S 4 is kept continuously off while during boost operation, S 1 remains on.Derived from the inverting buck-boost topology[19], the voltage balancer circuit is utilized to split the six-pulse dc-link voltage v xz into the two series connected dc-link voltages v xy and v yz , essential for unfolding operation.The operation of the balancer can be conceptualized as a buck operation, where v xz serves as the input voltage and v yz as the output.Consequently, the duty ratio of switch S 5 is given in TableII, varying between zero and one within each sector of operation.Fig. 5(a) depicts the dc-link voltages while Fig. 5(b) shows the corresponding waveforms of the NIBB duty cycle for boost operation and the balancer duty.

Fig. 5 .
Fig.5.Waveforms of the proposed unfolder system (Fig.4) showing (a) dclink voltages, (b) NIBB and balancer duty ratios, (c) dc-link currents, (d) balancer inductor current and its low-frequency component, (e) NIBB inductor current and its low-frequency component, and (f) powers processed by NIBB and voltage balancer for NIBB boost operation and a power factor of 0.9.

Fig. 6 .
Fig.6.Voltage based control scheme for the proposed powertrain.The motor control strategy provides the machine phase voltage references which are used to control the dc-dc as well as the unfolder stages.

Fig. 7 .
Fig. 7. Derivation of reference voltages for the NIBB and voltage balancer.(a) Motor phase voltage references from motor control strategy.(b) Maximum, median, and minimum of the phase voltage references.(c) References for the dc-link voltages.

Fig. 8 .
Fig. 8. Simulation results showing PI controller performance (a) and (b) without feed-forward duty and (c) and (d) with feed-forward duty.

Fig. 9 .
Fig. 9. Waveforms showing voltages blocked and currents carried by (a) transistor Q 1a and (b) transistor Q 2a of the T-type inverter as well as (c) the fundamental frequency switching signals of Q 1a and Q 2a .

Fig. 10 .
Fig. 10.Conventional two-stage EV powertrain comprising a bidirectional boost and a two-level voltage source inverter (VSI).

Fig. 12 .
Fig. 12.(a) 5 kW all-SiC based hardware prototype of the proposed converter and (b) corresponding weight distribution of various components.

Fig. 13 .
Fig. 13.(a) Measured efficiency (Hioki PW6001) of the proposed converter over the entire speed-torque region of the utilized induction machine.(b) Calculated loss breakdown at points A (760 rpm, 25 Nm) and B (1300 rpm, 20 Nm).
(a) represent the motor line-line voltage v ab , line current i a , estimated rotor speed in rpm N r,est , and estimated electromagnetic torque produced by the machine T em,est over the 400 s duration of the selected drive cycle for an input voltage of 350 V.The converter demonstrated accurate tracking of the changing speed reference under varying load conditions, without any instability issues.Fig. 14(b) and (c) show the converter ac and dc-link waveforms respectively during region 1 of the drive cycle.In this region, the motor operates at a low speed of 600 rpm (around 20 Hz ac), with a corresponding load torque of 13 Nm.Fig. 14(b) presents two line-to-line voltages and two line currents, while Fig. 14(c) illustrates the dc-link voltages v xy and v xz , along with the dc-dc stage inductor currents.With a peak line-to-line voltage of 220 V, the NIBB converter operates in buck mode for this region.

Fig. 14 .
Fig. 14.Experimentally measured waveforms of the proposed converter, operating with a 350 V dc input, demonstrating its dynamic performance.(a) The motor speed follows a standard drive cycle while the load is configured to emulate an EV load.(b) and (c) Detailed views of ac and dc waveforms during low-speed region (around 600 rpm/20 Hz).(d) and (e) Detailed views of ac and dc waveforms during high-speed region (around 1500 rpm/50 Hz).(f) Inductor currents of the dc-dc stage at rated speed and load illustrating ZVS-QSW operation.

Fig. 15 .
Fig. 15.Experimental waveforms depicting speed tracking in response to (a) a step change in speed from 600 rpm to 1200 rpm, and (b) a linear change from 600 rpm to 1200 rpm over two seconds.

TABLE III SYSTEM
SPECIFICATIONS AND SELECTED PASSIVE COMPONENT VALUES

TABLE V SELECTED
COMPONENTS BASED ON DESIGNED VALUES