A 0.4–1.8-GHz Quarter-Rate Subsampling Mixer-First Direct Down-Conversion RF Front-End

Subsampling down-conversion has not been a popular choice for mixer-first RF front-ends for two interdependent reasons. One, the subsampling down-conversion is inherently heterodyne in nature. Two, as a consequence to one, the passive mixer transparency property can not be exploited for providing impedance matching at the RF port by impedance translation. In this work, an eight-path quarter-rate subsampling (QRSS) mixer-first direct down-conversion architecture is proposed to address these issues. The proposed architecture simultaneously achieves quadrature direct down-conversion and impedance matching by using the third harmonic of the QRSS frequency, <inline-formula> <tex-math notation="LaTeX">$f_{s}$ </tex-math></inline-formula>. The impedance matching is achieved by exploiting the eight-path passive mixer transparency property. Compared to RF sampling receivers, this architecture employs a sampling frequency <inline-formula> <tex-math notation="LaTeX">$f_{s}$ </tex-math></inline-formula> three times lesser than <inline-formula> <tex-math notation="LaTeX">$f_{\text {RF}}$ </tex-math></inline-formula>, saving on the power consumption of nonoverlapping clock generation, distribution circuits, and frequency synthesizer. A test chip is fabricated in 1.2-V, 65-nm CMOS with an active area of 0.32 mm2. The subsampling eight-path mixer, baseband low-noise amplifier (LNA), and <inline-formula> <tex-math notation="LaTeX">${\text{g}_{m}}$ </tex-math></inline-formula>-cell consume a power of <inline-formula> <tex-math notation="LaTeX">$800 \mu \text{W}$ </tex-math></inline-formula>, 23 mW, and 3 mW, respectively, for a target bandwidth of 90 MHz. Nonoverlapping clock generation circuit consumes 2–9.2 mW, over the band 0.4–1.8 GHz. The receiver has a double sideband (DSB) noise figure of 4.7 dB, a conversion gain of 22 dB, an in-band (IB)-IIP3 of −1 dBm, and OB-IIP3 of +8 dBm.

frequency band by tuning sampling frequency.Hence, these reconfigurable radios cover a complete wireless communication standard under sub-6 GHz for various applications such as smart utility networks (SUNs), rail communications and control (RCC), healthcare, and industrial monitoring, where better coverage and long battery life are important.
The RF sampling-based switch-capacitor receiver RF frontends require the sampling frequency ( f s ) greater than or equal to the input RF ( f RF ) [2], [3], [4], [5].On the other hand, the subsampling down-conversion RF front-ends [6], [7] requires a sampling frequency ( f s ) less than the input RF signal frequency ( f RF ) and greater than twice the bandwidth of the input RF signal frequency leading to the reduced power consumption of the frequency synthesizer, nonoverlapping clock generation, and distribution circuitry.Therefore, the subsampling down-conversion is a good alternative to RF sampling down-conversion for implementing reconfigurable switch-capacitor mixer-first RF front-ends for low-power and wide frequency-band applications.However, the subsampling down-conversion is not a popular choice for implementing in mixer-first receivers for the following two reasons.
First, the down-conversion is to a nonzero-IF, as it is wellknown that subsampling down-conversion is inherently heterodyne in nature [8].Second, the passive mixer transparency property cannot be exploited like in RF sampling to realize impedance matching.Hence, the mixer-first receivers reported in the literature employed RF sampling down-conversion [4], [9] even though subsampling down-conversion receivers [6], [10] require low sampling frequency compared to RF sampling receivers, leading to less complex and low-power clocking circuitry.The recent work on subsampling mixer-first RF front-end [7] offers low noise figure and impedance matching.However, it is a nonzero-IF architecture.Therefore, this work addresses two major issues, which are interdependent on each other for arriving at a mixer-first subsampling downconversion; one is nonzero-IF down-conversion, and the other is impedance matching at the RF port.
In this work, a reconfigurable switch-capacitor mixer-first subsampling direct down-conversion receiver [11] is proposed to address the above two issues.In the first issue, nonzero IF down-conversion is addressed by employing an eightpath switch-capacitor subsampling quadrature direct downconversion using the third harmonic of the quarter-rate subsampling (QRSS) frequency, f s , along with harmonic recombination.In the second issue, the lack of impedance matching at the RF port is addressed by exploiting the transparency property of the eight-path passive mixer at the third harmonic of f s .This QRSS frequency is much lower than the sampling frequency that would be needed if implemented by RF sampling principles.This frequency plan significantly saves the clocking circuitry power consumption.Thus, the proposed architecture deploys a unique subsampling scheme for realizing the direct down-conversion with the third harmonic of the QRSS frequency.
To validate the proposed ideas, a test chip is fabricated in a 1.2-V, 65-nm CMOS technology.The prototype occupies an active area of 0.32 mm 2 .The measurement results show that the subsampling eight-path mixer consumes a power of 800 µW over the frequency band 0.4-1.8GHz with 90-MHz bandwidth.The receiver has a double sideband (DSB) noise figure of 4.7 dB, a conversion gain of 22 dB, an in-band (IB)-IIP 3 of −1 dBm, and OB-IIP 3 of +8 dBm along with the 50matching at the RF port of the mixer.
The rest of this article is organized as follows.Section II presents a low-power paradigm of the subsampling downconversion, proposed QRSS direct down-conversion RF front-end architecture, frequency plan, and harmonic recombination scheme along with the performance analysis of the RF front-end.Section III presents the proposed impedance matching scheme.Circuit-level implementation of the proposed RF front-end architecture is presented in Section IV.Section V presents the measured performance of subsampling direct down-conversion mixer-first receiver architecture, and Section VI concludes this article.

II. SUBSAMPLING DIRECT DOWN-CONVERSION MIXER-FIRST RF FRONT-END ARCHITECTURE
This section presents the subsampling down-conversion low-power paradigm and the architecture of the proposed QRSS direct down-conversion mixer-first RF front-end.In addition, the frequency plan, eight-path subsampling direct down-conversion mixer, and harmonic recombination schemes are explained.Moreover, the performance analysis of the proposed RF front-end in terms of conversion gain, noise figure, and linearity is presented.

A. Subsampling Down-Conversion: A Low-Power Paradigm
The advancements in the technology scaling improved the switching performance of the transistor; hence, the switchcapacitor RF front-end circuits, such as passive N -path mixers and N -path filters, offer reconfigurable operation over a wide frequency range.However, extending the operation to higher RFs leads to an increase in the overall power budget of the receiver due to the rapid increase in power consumption of the frequency synthesizer, nonoverlapping multiphase clock generation, and distribution circuitry.Sampling-based N -path receivers [3], [4], [12], [13], [14], [15] employ clock dividers to generate precise multiphase nonoverlapping clocks.These dividers require a clock frequency of N f s /2 for generating nonoverlapping clocks with a frequency, f s .Therefore, the power consumption of multiphase nonoverlapping clock generation and distribution in RF sampling-based receivers is no longer negligible, as shown in Fig. 1(a).The power consumption of the clocking circuit surpasses the receiver chain power consumption as the operating frequency increases [3], [4], [13], [14], [15]; hence, it limits the frequency range of operation.On the other hand, implementing the downconversion using a subsampling mixer requires a sampling frequency less than the input RF, thus offering a solution to the power consumption issue [12].Supporting this statement, Fig. 1(b) shows the power consumption of frequency generation circuits with respect to the operating RF [16], [17], [18], [19], [20], [21], [22], [23].It is evident from Fig. 1(b) that as the sampling frequency of a mixer reduces, the power consumption of the clocking circuitry reduces significantly.
In addition, a recent work [24] on lower power bounds for clock generation circuits also emphasized the impact of increased power consumption at higher operating frequencies of wireless and wireline communication systems.The voltagecontrolled oscillator (VCO) power consumption grows with the square of the clock frequency, f s , specifically, the P VCO ∝ f 2 s .This trend of increased power consumption makes it challenging to design clock generation at a higher frequency of operation for low-power applications.However, subsampling down-conversion requires a sampling frequency less than the input RF, reducing the clock generation's power budget For a given f RF , the power consumption of VCOs for the RF sampling down-conversion (P VCO,RF ), subsampling (P VCO,SS ), and quarter-rate subsampling (QRSS) (P VCO,QRSS ) are given by (1a)-(1c), respectively, where k = 1, 2, 3, . . .The ratio of power consumption of the VCOs for both the subsampling down-conversion techniques is normalized with the P VCO,RF and shown in Fig. 2. For a given f RF , compared with the RF sampling, the subsampling down-conversion technique and QRSS technique save the power of the VCO by more than 36% and 89%, respectively.Therefore, subsampling downconversion receiver architectures offer a solution to reduce the power budget of the clock generation and distribution circuits.

B. QRSS Direct Down-Conversion Architecture
The block diagram of the proposed QRSS mixer-first receiver RF front-end architecture is shown in Fig. 3.An offchip RF filter selects the frequency band with a bandwidth of 90 MHz present at the carrier frequency between 0.4 and 1.8 GHz and suppresses the out-of-band blockers present at the odd harmonics of f s .Then, the eight-path QRSS direct downconversion mixer translates the input RF signal to a zero-IF.The translated baseband signal gets amplified by the baseband low-noise amplifiers (BBLNAs).In addition, the BBLNA provides the required baseband impedance, which is translated to the RF port of the mixer to match 50-antenna impedance.The BBLNA outputs are further amplified and duplicated by g m -cells.The g m -cell outputs are recombined to obtain the third harmonic quadrature down-conversion and to attenuate the fundamental-and fifth-harmonic down-conversions.The major blocks, mixer and BBLNA of the proposed RF frontend, are implemented with process scalable components such as switches, capacitors, and inverters, making the RF front-end a digitally intensive architecture.

C. Frequency Plan
In subsampling down-conversion, for a given input RF signal with frequency f RF , the sampling frequency F s is selected from (2a), and the IF outputs are generated at odd harmonics of F s /4 [8] [11].
where k = 1, 2, 3, . . .and n = 1, 3, 5, . . .A single-path switch-capacitor mixer, shown in Fig. 4(a), serves the purpose of subsampling down-conversion; however, it has a high noise figure and does not provide quadrature direct down-conversion and impedance matching [6].On the other hand, an N -path subsampling down-conversion mixer approach using F s offers a low noise figure, quadrature downconversion, and impedance matching [7].However, the downconversion is to a nonzero IF, and the effective sampling frequency, f s,eff , of the N -path approach increases to N F s .Therefore, to reduce the effective sampling frequency of N -path implementation and to achieve direct down-conversion to zero-IF, this work employs an eight-path mixer with the third harmonic of the QRSS frequency, f s , given by (2b), where f BB is the baseband frequency, f IF is the intermediate frequency, and n represents the harmonic of f s .Thus, the proposed architecture deploys a unique subsampling scheme compared to RF sampling for realizing the direct downconversion and saving on the clocking circuitry power consumption.It is also evident from (1a) and (1c) that for a given input RF signal of frequency f RF , the power consumption of VCO for RF sampling-based four-path mixer scheme is proportional to (2 f RF ) 2 , and for RF sampling-based eightpath mixer scheme, it is proportional to (4 f RF ) 2 .On the other hand, the power consumption of VCO for the proposed QRSS is proportional to (4 f RF /3) 2 .Hence, when compared with the VCO power consumption of the four-path and eight-path RF sampling down-conversion schemes, the proposed QRSS down-conversion scheme saves the VCO power by 55% and 89%, respectively.
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D. Eight-Path Direct Down-Conversion Mixer and Harmonic Recombination Scheme
The eight-path switch-capacitor subsampling mixer is shown in Fig. 4(b).Each path of the mixer is excited by QRSS frequency, f s , with 12.5% duty-cycle nonoverlapping clocks, S 0 • -S 315 • .The downconverted baseband output voltage on the capacitor of mth path of the mixer is denoted by V bb,m , and it is calculated by solving the charge balance equation given as follows [25]: The solution for V bb,m for V RF = A cos (ω RF t + φ) is given by the following equation, where Q m is the charge on the mth capacitor, ω RF = nω s , and n = 1, 3, 5, . . .
where R ′ s = (R s + R sw ), R s is the antenna impedance, R sw is the ON-resistance of the switch, and R BB is the real component of baseband stage input impedance.
The eight-path mixer output voltages V bb,0 -V bb,7 are obtained by substituting the phase of the corresponding sampling clock in (4).The resultant baseband output voltages experience a phase shift of (n × 360/N ) • , where N = 8.It means that the eight baseband voltages corresponding to the fundamental, third, and fifth harmonics of f s experience a phase shift 45 • , 135 • , and 225 • , respectively, as shown in Fig. 5. Therefore, to obtain the quadrature outputs for third harmonic down-conversion, V bb,0 -V bb,7 are recombined as given in (5a) with uniform-weighing gain.The resultant simplified I and Q output expressions are given by (5b), for the direct down-conversion of the RF signal present at the third harmonic of f s to the zero-IF.Similarly, for the same recombination scheme, the analytical I and Q output equations for the fundamental-and fifth-harmonic down-conversions are given by (5c) where the term K = (8R BB sin((nπ/8))/π(R BB + 8R ′ s )).To verify the proposed QRSS direct down-conversion scheme, time-domain simulations are performed for an f RF of 1490 MHz and f s of 490 MHz.The time-domain differential quadrature baseband outputs and the frequency spectrum of the in-phase outputs are shown in Fig. 6(a) and (b), respectively.The frequency spectrum contains desired downconverted baseband output, f RF − 3 f s at 20 MHz and down-conversions from the fundamental and fifth harmonics of f s at 1 GHz and 960 MHz, respectively, as shown in Fig. 7(a).

E. Conversion Gain
In the proposed QRSS direct down-conversion scheme, the down-conversion is implemented by the third harmonic of f s ; hence, the conversion gain of the RF front-end is defined as the ratio of the amplitude of the signal down-converted to zero-IF to the RF signal amplitude at the 3 f s .However, in addition to 3 f s , it is important to know the conversion gain of the front-end for blockers present at the fundamental, f s , and fifth harmonics, 5 f s , as these blockers are downconverted to zero-IF, as shown in Fig. 7(b).This is quantified by  (V I /Q,(1,5) /V I /Q,3 ) using (5b), and (5c) gives the magnitude of rejection of the blockers at f s or 5 f s with respect to the desired third-harmonic down-conversion.The magnitude of the attenuation for the fundamental, f s , to third harmonic, 3 f s , is 12.5 dB, and for the fifth harmonic, 5 f s , to third harmonic, 3 f s , is 5 dB.However, the blockers present at the fundamental and fifth harmonics of f s are well-separated with respect to 3 f s and they are already attenuated sufficiently by the frontend RF filters usually available in a practical RF system.
In the proposed QRSS RF front-end, BBLNA, g m -cell, and eight-path switch-capacitor mixer provide a voltage gain of 16, 6.5, and −0.5 dB, respectively.To verify the conversion gain of the proposed QRSS mixer-first RF front-end, SpectreRF simulations PSS and PXF are performed for an f RF of 1470 MHz and f s of 490 MHz and for the harmonic scheme shown in Fig. 7(a).The simulation result shows that the conversion gain of the RF front-end for the 3 f s is 22 dB, as shown in Fig. 8.

F. Noise Figure
The equivalent noise model of the proposed RF front-end is shown in Fig. 9.The RF front-end contains the following major sources of noise: noise due to the resistance of the MOS switch, R sw , and baseband stage noise including baseband stage resistance, R BB , BBLNA, and g m -cell.The noise figure of the RF front-end for nth-harmonic down-conversion is given by the following equation, which is derived based on LTV analysis given in [26]: where A HRC is the harmonic recombination factor, 1 + √ 2 for n = 3, 5 and 1 − √ 2 for n = 1, N is the number of mixer paths, and v 2 n,R s and v 2 n,R sw are noise contributions from the source resistance, R s , and switch resistance, R sw , respectively.v 2 n,BBLNA and v 2 n,g m , are input referred noise of the BBLNA and g m -cell, respectively.R BB is the baseband stage impedance, and A ′ v is the voltage gain of the first stage of BBLNA.The noise figure of the RF front-end, given by ( 6), shows that the noise figure increases at higher harmonics of sampling frequency f s even though it requires a low sampling frequency and reduces the clocking circuitry's power consumption.On the other hand, increasing the number of paths in an Npath mixing scheme offers a low noise figure for a selected harmonic down-conversion.It means that for a selected harmonic down-conversion, the eight-path mixer offers a lower noise figure than the four-path mixer.In addition, the proposed harmonic recombination scheme provides additional gain which further offers low-noise figure at the third harmonic downconversion compared to a traditional implementation [2].
To quantify the effect of the proposed recombination scheme on the noise figure, the theoretical minimum noise figure of the traditional eight-path mixer implementation and the proposed schemes are calculated, using (6), for the fundamental, third, and fifth harmonics of f s , as shown in Fig. 10.The analytical results show that the noise figure of an eight-path implementation using traditional harmonic recombination scheme achieves a minimum noise figure of 0.2, 2.1, and 7 dB at fundamental, third, and fifth harmonics of f s , respectively.On the other hand, the same eight-path implementation with the proposed harmonic recombination scheme achieves a minimum noise figure of 13, 0.47, and 5 dB at fundamental, third, and fifth harmonics of f s , respectively, while using a sampling frequency three times less than the traditional case.These results confirm that the proposed eight-path implementation with QRSS third harmonic down-conversion offers a lower noise figure than a traditional implementation.Therefore, an eightpath mixer with QRSS and third harmonic down-conversion is implemented in this work.To calculate the actual noise figure of the RF front-end, the analysis is further extended by adding the baseband stage noise contribution and it is found that the noise figure of the RF front-end is increased by 2.1 dB in both cases after including the noise contribution from the baseband stage, as shown in Fig. 10.
The noise figure of the proposed RF front-end is obtained for an R sw of 10 , R BB of 250 , A v,BBLNA of 16 dB, v 2 n,BBLNA of 0.7 nV/(H z) 1/2 , and v 2 n,gm of 1.4 nV/(H z) 1/2 using (6).The obtained DSB noise figure of the proposed RF front-end is 2.5 dB for the third-harmonic down-conversion, and 15.93 and 6.94 dB for the fundamental-and fifthharmonic down-conversions, respectively.It shows that, due to the proposed harmonic recombination scheme, there is an improvement in the noise figure for the third-harmonic down-conversion rather the traditional eight-path mixer downconversion and combining scheme.
To verify the noise analysis presented above, SpectreRF PSS and PSP simulations are performed for the proposed QRSS mixer-first RF front-end.The SpectreRF simulation results show that the RF front-end, including an eight-path mixer, Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.BBLNAs, and g m -cells, has a DSB noise figure of 4.6 dB for the third-harmonic down-conversion, and 17.4 and 9.25 dB for fundamental-and fifth-harmonic down-conversions, respectively, for an f s of 490 MHz.From this analysis, it is evident that the QRSS architecture achieves a noise figure comparable with the RF sampling front-end.
In addition, to verify the effect of the blocker on the noise performance of the proposed RF front-end, an in-band blocker is introduced with a 20-MHz offset for an RF of 1.47 GHz with an amplitude varying from −50 to −10 dBm.The blocker has no effect on the noise performance of the RF front-end till the blocker amplitude of −16 dBm, and the noise figure is increased to 8.4 dB when the amplitude of the blocker is increased to −10 dBm.

G. Linearity and Power Consumption
SpectreRF QPSS and QPAC simulations are performed to estimate the IB-IIP 3 of the QRSS direct down-conversion RF front-end for two input tones at 1.47 and 1.471 GHz with 1-MHz offset, and sampling frequency of 490 MHz.The resultant IIP 3 of the proposed subsampling zero-IF receiver is −1 dBm.In this work, the linearity of the BBLNA is optimized to provide a −1-dBm IIP 3 , which has increased the power consumption of BBLNA to 23 mW at 1.2-V supply.

III. IMPEDANCE MATCHING SCHEME
In a switch-capacitor mixer-first receiver, the passive mixer transparency facilitates the input impedance matching by frequency translating the output/baseband stage impedance to the input/RF port of the mixer [25].In RF sampling down-conversion, each switching path of the N -path mixer conducts for 1/N th of the sampling period (1/ f s ).Hence, the RF port sees baseband impedance at every instance of the sampling period, and it gets upconverted to the sampling frequency f s at the RF port, as shown in Fig. 11(a).However, for the subsampling down-conversion, f s is less than f RF .Therefore, an additional IF stage matching scheme is required to translate the impedance to the RF port of the mixer [7] as shown in Fig. 11(b).On the other hand, employing  the proposed subsampling down-conversion scheme translates baseband impedance to f RF using the third harmonic of QRSS frequency, as shown in Fig. 11(c).Therefore, the proposed scheme eliminates the need for an additional IFstage impedance matching network for subsampling downconversion receivers.
The equivalent model of differential N -path mixer is represented by the linear time-invariant (LTI) model, as shown in Fig. 12.The equivalent input impedance at the RF port of the mixer for nth harmonic of the sampling frequency is given by the following equation [25], [26]: where Z RB represents the upconverted baseband impedance and Z sh represents the folding shunt impedance at nth harmonic, R in,BBLNA represents the input impedance of the BBLNA, and C H is the sampling capacitor of the mixer.It is evident from ( 7) that the baseband impedance is frequencytranslated to switching frequency " f s " and its harmonics.However, as the "n" increases, Z sh decreases, and if it becomes less than 50 , it is not possible to match the antenna impedance.For the four-path mixer, the Z sh is less than 50 at all the harmonics other than fundamental frequency f s .Hence, 50-impedance matching is only possible at the fundamental, f s .On the other hand, increasing the number of paths to eight, the magnitude of the shunt impedance Z sh surpasses 50 for the fundamental and third harmonics of f s .This property of the N -path mixer allows matching the input impedance at the fundamental and third harmonics of f s by tuning baseband impedance R in,BBLNA .Therefore, an eight-path subsampling switch-capacitor mixer is employed for realizing impedance matching using the third harmonic of f s .SpectreRF PSS, PSP simulations are performed to validate the input impedance obtained from the analytical equations.In the proposed QRSS mixer-first receiver architecture, the BBLNA provides the required baseband impedance to match 50 at the RF port of the mixer.The simulated real and imaginary components of the input impedance are shown in Fig. 13(a) and (b) for an f RF of 1.476 GHz and f s = 492 MHz, respectively.The analytical and simulation results of input return loss, S 11 , shown in Fig. 13(c) confirm that the input impedance matches to 50 at the third harmonic of f s and poor matching at the fundamental and fifth harmonics of f s .

IV. CIRCUIT IMPLEMENTATION
This section explains the circuit-level implementations of the building blocks of the proposed QRSS mixer-first direct down-conversion RF front-end architecture along with the nonoverlapping clock generation scheme.The complete architecture along with the transistor-level implementation of the circuits and corresponding transistor dimensions are shown in Fig. 14.

A. Eight-Path Switch-Capacitor Mixer
The differential eight-path passive mixer shown in Fig. 14(a

B. Baseband Low-Noise Amplifier
The circuit diagram of the CMOS inverter-based noise canceling BBLNA is shown in Fig. 14(b).First-stage of the amplifier is designed to provide the required baseband impedance, given by the following equation, which is translated to RF port by the mixer to match 50 : where R o = r o5,6 ∥r o1,2 and G m = g m1,2 + g m5, 6 .The second stage of the amplifier is designed to cancel the first-stage noise.
The noise canceling is achieved by matching the gain provided by second-stage nMOS (M 3,4 ) with the gain provided by the first stage together with the second-stage pMOS (M 7,8 ).The total gain of the amplifier is given by the following equation, where R F is the feedback resistor, and The linearity of the BBLNA limits the mixer-first RF frontend linearity; hence, to improve the linearity of the BBLNA, the IM3 products generated by the first stage are canceled by adjusting the g m,M3 .Therefore, to adjust the g m,M3 , an auxiliary path with tuning option of V cntrl is added with an expense of power consumption.For a tuning voltage, V cntrl , of 400 mV, the BBLNA provides an IIP 3 of −1 dBm.Increasing V cntrl reduces the power consumption of the BBLNA; however, this affects the linearity of the RF front-end.
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C. g m -Cells and Harmonic Recombination
The circuit diagram of the g m -cell is shown in Fig. 14(c) which is a pMOS differential amplifier with a resistive load that provides a second stage of amplification for the baseband signal.The standalone g m -cell offers a 6.5-dB voltage gain.In the proposed eight-path operation, all the eight outputs are recombined with the uniform weighing gains of the g m -cells, as explained in Section II-D, 5a, to obtain quadrature outputs using the third-harmonic down-conversion.

D. Measurement Buffer
The circuit diagram of the BB stage measurement buffer, shown in Fig. 14(d), is designed using 2.5 V supply transistors and provides an IIP 3 of 32 dBm, −1.4 dB loss, consumes a 3 mW power, 50 impedance at the output.The buffer with high linearity eliminates the need for de-embedding the buffer nonlinearity in the measurements.

E. Nonoverlapping Clock Generator
The eight-path 12.5% nonoverlapping clock scheme for the proposed RF front-end is shown in Fig. 14(e).An onchip single-to-differential converter is employed to convert the external single-ended clock to a differential clock.These differential clock phases are divided by D-latch-based clock dividers, and the divider output phases are combined using combinational logic to generate nonoverlapping clock phases with the required duty cycle.

V. MEASUREMENT RESULTS
The proposed QRSS direct down-conversion mixer-first RF front-end test chip is fabricated in 1P9M TSMC 65-nm CMOS technology.The RF front-end architecture occupies an active area of 0.32 mm 2 .The test chip is directly attached to the test PCB using the chip on board (COB) method and wirebonded.The bare die is covered by epoxy to protect wirebonded connections, as shown in Fig. 15(a).The test PCB is a four-layer FR4 PCB with co-planar 50-RF and baseband paths.
The block diagram of the measurement setup is shown in Fig. 15(b), along with the measurement equipment.The test chip is powered by an external supply of 1.2 V for core analog/RF, and 2.5 V for the measurement buffers and I/O pads.A separate 1.2-V supply with a ground plane is used for shows that the input RF down-conversion to 20 MHz and leakage of f s at 480 MHz.In addition, the fundamental and fifth harmonics of f s downconverting the f RF of 1460 to 940 and 980 MHz, respectively, are attenuated by 36 and 43 dB with respect to the third-harmonic down-conversion.The first and fifth harmonics are attenuated by 36 and 43 dB compared to the third harmonic due to the poor conversion gain of the mixer for the first and fifth harmonics of local oscillator (LO), as depicted in Fig. 7(a).In addition to the f RF at 3 f s , the mixer also translates the interferers present at the f s and 5 f s to the baseband, with conversion gains as explained in Section II-E, quantified by (V I /Q,(1,5) /V I /Q,3 ) using (5b) and (5c).To verify this, an RF signal is applied at the f RF equals to 3 f s along with the interferer f int at the f s or 5 f s with the same amplitude.The measured baseband spectrum for the desired signal at f RF of 851 MHz and the interferer at f int of 302 MHz with an f s of 280 MHz translates to baseband with the desired signal located at 11 MHz and    show that the proposed harmonic recombination attenuates the down-conversion of the interferers at the fundamental and fifth harmonics of f s by 17 and 7 dB, respectively, the reason for better harmonic rejection compared to simulation results due to higher return loss at the reported frequency of 851 MHz.Therefore, the proposed harmonic recombination provides an additional harmonic rejection along with the RF filter for outof-band harmonic blockers.
2) Conversion Gain and Noise Figure : The conversion gain of the subsampling direct down-conversion RF frontend is measured for an f RF range of 0.4-1.8GHz by tuning the f s from 0.13 to 0.6 GHz.The RF front-end has a measured conversion gain of 22 dB with a maximum of 3-dB variation throughout the band, as shown in   3) Input Return Loss, S 11 : The input impedance of the receiver is implemented by exploiting the transparency property of the passive mixer, as explained in Section IV.The switch-capacitor mixer translates the baseband impedance to the RF port of the mixer and is matched to 50 at the third harmonic of f s by tuning the input impedance of the baseband LNA.In the measurements, the input impedance matching is verified by one-port S 11 measurements.Fig. 20(b) shows the S 11 measured for an f RF from 0.4 to 1.8 GHz by varying the f s from 0.13 to 0.6 GHz.The measured S 11 is better than −10 dB throughout the 0.4-1.8-GHzfrequency range.Similarly, to verify the impedance matching at desired third harmonic and undesired fundamental and fifth harmonics of f s , the S 11 is measured for an f s of 500 MHz and its corresponding harmonics.Fig. 20(a) shows that the measured S 11 is −25 dB at the 3 f s , −10 dB at the f s , and −12 dB at the 5 f s .These results ensure that the proposed impedance matching scheme provides 50-impedance to the RF port of the mixer using the third harmonic of f s .The S 11 notch is shifted from the center frequency due to the capacitive parasitics, and this effect is increased as the f RF is increased to 2 GHz.
4) IIP 3 and Power Consumption: The IIP 3 of the subsampling direct down-conversion is measured by the two-tone The switch-capacitor blocks of the RF front-end, eightpath down-conversion mixer consume the power of 800 µW.This low power consumption makes the proposed QRSS mixer-first RF front-end is suitable for low-power applications.In addition, the enhancement of IIP 3 performance has increased the BBLNA power consumption.The measured power consumption of BBLNA is 23 mW at V c = 0.4 V.The nonoverlapping clock generation and distribution for the eightpath mixer consumes 2-9.2 mW for an f s of 0.13-0.6GHz.The measurement buffer consumes 2.5 mW of power from the 2.5-V supply.
The performance comparison of the proposed QRSS direct down-conversion RF front-end with the state-of-the-art subsampling and RF sampling receivers is presented in Table I.Table I also additionally includes a comparison between highperformance and low-power receivers in the subsampling and RF sampling class of RF front-ends.The proposed RF frontend provides a reconfigurable operation from 0.4 to 1.8 GHz using an f s of 0.13-0.6GHz.The measured noise figure of the RF front-end is 4.7 dB for a conversion gain of 22 dB, which is the lowest among the subsampling RF front-end architectures [6], [10].In addition, the noise figure achieved by the proposed RF front-end is comparable with the RF sampling counterparts [2], [3], [4], [9], [27], [28], [29], [30] using a sampling frequency equal to one-third of RF sampling counterparts while achieving bandwidth of 90 MHz, IB-IIP 3 of −1 dBm, and OB-IIP 3 of +8 dBm.Therefore, the proposed architecture falls under the class of high-performance, low-power subsampling RF front-ends.On the other hand, there is another class of RF front-ends, which are mainly targeted for narrowband applications [27], [28], [29], [30].These narrowband RF front-ends only offer a bandwidth of 1-4 MHz while offering very low power consumption.To achieve very low power, these RF front-ends employed an on-chip transformer at the front-end before mixer stage to realize the gain with an area overhead and poor IB-IIP 3 .Moreover, these narrowband RF sampling front-ends consume VCO power 55% more compared to the proposed QRSS frontend.In addition, the proposed impedance matching scheme using the harmonics of f s eliminates the need for an additional matching network for subsampling RF front-ends [6], [7], [10].Therefore, this is the first subsampling mixer-first RF front-end demonstrating the direct down-conversion, low noise figure, and impedance matching for 0.4-1.8-GHzwideband operation with a bandwidth of 90 MHz and a +8-dBm OB-IIP 3 .

VI. CONCLUSION
In this work, a unique method of QRSS direct downconversion RF front-end architecture along with RF-port impedance matching is presented.A proof-of-concept test chip is fabricated in 1.2-V, 65-nm CMOS to validate the proposed ideas.The measurement results show that the proposed subsampling down-conversion scheme is a suitable candidate for implementing low-power reconfigurable mixer-first RF frontends.

Fig. 1 .
Fig. 1.Power consumption of the: (a) nonoverlapping clock generation circuits and (b) frequency synthesizers with respect to the operating frequency.

Fig. 5 .
Fig. 5. Vector representation of the baseband voltages of the eight-path mixer with respect to fundamental, third, and fifth harmonics of the sampling frequency, f s .

Fig. 6 .
Fig. 6.Proposed RF front-end: (a) time-domain output waveforms and (b) in-phase output spectrum for an f RF of 1490 MHz and f s of 490 MHz.

Fig. 7 .
Fig. 7. Harmonic down-conversion of the mixer: (a) for signal present at the third harmonic of the sampling frequency, f s and (b) for signal present at the corresponding harmonic of the sampling frequency, f s .

Fig. 8 .
Fig. 8. Conversion gain of the RF front-end for an f RF of 1470 MHz and f s of 490 MHz.

Fig. 9 .
Fig. 9. Equivalent noise model of the proposed RF front-end.

Fig. 10 .
Fig. 10.Noise figure of the eight-path traditional and proposed RF front-end at the fundamental, third, and fifth harmonics.

Fig. 13 .
Fig. 13.Input impedance of the subsampling mixer-first direct down-conversion RF front-end for an f RF of 1470 MHz and f s of 490 MHz, showing the: (a) real part; (b) imaginary part; and (c) S 11 .
) is employed in this work for down-conversion.The MOS switches are implemented with a minimum length of 60 nm, and the widths are chosen to have an ON-resistance, R sw , of 10 .Each switching path is excited by one of the 12.5% duty-cycle nonoverlapping clock phases, S 0 • -S 315 • with QRSS frequency, f s .Each path of the mixer conducts for ((1/8))th of the sampling period and downconverts the input RF signal onto hold capacitors, C H 0 -C H 7 .The eight outputs of the mixer are directly coupled to the input of the BBLNAs.The direct coupling of the mixer outputs to BBLNA forces the voltage at the source and the drain terminals of the mixer switches to the same as the gate voltage of the M 1,2 and M 5,6 of BBLNA.Therefore, the clock inputs are applied at the gate terminal of the switches with additional biasing voltage V b3 .

Fig. 16 .
Fig. 16.Measured: (a) transient baseband in-phase and quadrature outputs downconverted to 1 MHz for an f RF of 1462 MHz and f s of 487 MHz and (b) spectrum at the baseband for an f RF of 1460 MHz and f s of 480 MHz.

Fig. 17
Fig. 17.Measured baseband output spectrum of the RF front-end for an f s of 280 MHz and f RF of 851 MHz in the presence of interferer, f int at the: (a) fundamental and (b) fifth harmonic of f s .

Fig. 18 .
Fig. 17.Measured baseband output spectrum of the RF front-end for an f s of 280 MHz and f RF of 851 MHz in the presence of interferer, f int at the: (a) fundamental and (b) fifth harmonic of f s .
(a).Similarly, Fig.17 (b) shows the frequency translations from the third and fifth harmonics of f s to baseband for f RF of 851 MHz and f int of 1422 to 11 and 22 MHz, respectively.These results

Fig. 18 .
To estimate the bandwidth, the conversion gain is measured by varying the f RF around 1470 MHz, while keeping the f s at 490 MHz, as shown in Fig. 19.The result shows that the RF front-end has a conversion gain of 21 dB at 1470 MHz with an estimated 3-dB bandwidth of 90 MHz.The noise-figure measurement setup of the subsampling direct down-conversion mixer-first RF front-end is shown in Fig. 15.The noise figure is measured for the input RF range

Fig. 19 .
Fig. 19.Measured conversion gain for an f RF of 1470 MHz and f s of 490 MHz.

Fig. 20 .
Fig. 20.(a) Measured S 11 for an input RF, f RF of 1.5 GHz, and sampling frequency, f s of 500 MHz.(b) Measured S 11 with respect to f RF and its corresponding f s .

Fig. 21 .
Fig. 21.Measured IIP 3 : (a) at an f RF of 1472 MHz, with the second tone at 1-MHz offset and f s of 490 MHz and (b) for varying f for an f RF of 1460 MHz.

TABLE I PERFORMANCE
SUMMARY AND COMPARISON WITH THE STATE-OF-THE-ART RF FRONT-ENDS