Wide Electrical Tunability of the Valley Splitting in a Doubly Gated Silicon-on-Insulator Quantum Well

The valley splitting of 2D electrons in doubly gated silicon-on-insulator quantum wells is studied by low temperature transport measurements under magnetic fields. At the buried thermal-oxide SiO₂ interface, the valley splitting increases as a function of the electrostatic bias <i>δn</i> = <i>n</i>_<i>B</i> – <i>n</i>_<i>F</i> (where <i>n</i>_<i>B</i> and <i>n</i>_<i>F</i> are electron densities contributed by back and front gates, respectively) and reaches values as high as 6.3 meV, independent of the total carrier concentration of the channel. We show that <i>δn</i> tunes the square of the wave function modulus at the interface and its penetration into the barrier, both of which are key quantities in a theory describing interface-induced valley splitting, and is therefore the natural experimental parameter to manipulate valleys in 2D silicon systems. At the front interface, made of a thin “high-k” dielectric, a smaller valley splitting is observed, adding further options to tune the valley splitting within a single device.