Inverter With Paralleled Modules to Extend Current Capacity and Combat Motor Overvoltage in SiC-Based Adjustable Speed Drives

This article proposes a quasi-three-level (Q3L) pulsewidth modulation (PWM)-based module-parallel inverter to address two major issues of deploying SiC mosfets in high-power cable-fed adjustable speed drives. First, the maximum output power of SiC inverters is limited due to the lack of high current rating silicon carbide (SiC) devices, which cannot satisfy the demand of high-power applications, such as heavy-duty electric vehicles and more electric airplanes. The second issue comes from the fast-switching speed of SiC mosfets, where power cables act like transmission lines under steep rising/falling voltages (high $dv/dt$), with back-and-forth voltage reflections that result in serious overvoltage oscillations at motor terminals. To address these issues, a SiC module-parallel inverter is adopted with elevated current capacity, where the phase voltage is maintained at the midpoint of a coupled inductor connected to the output nodes of each paralleled half-bridge module. By actively controlling the switching delay between the paralleled half-bridge legs, Q3L PWM waveforms are generated at the inverter output nodes that can mitigate the motor overvoltage due to the voltage reflections through power cables. An active current control technique is also proposed to facilitate the current balance between the paralleled half-bridge legs. The proposed Q3L PWM-based module-parallel inverter is experimentally verified using a SiC-based cable-fed motor drive system. The results show that the proposed approach can extend the current capabilities of SiC devices as well as mitigate motor overvoltage, enabling the adoption of SiC devices in high-power motor drives.

Abstract-This article proposes a quasi-three-level (Q3L) pulsewidth modulation (PWM)-based module-parallel inverter to address two major issues of deploying SiC MOS- FETs in high-power cable-fed adjustable speed drives.First, the maximum output power of SiC inverters is limited due to the lack of high current rating silicon carbide (SiC) devices, which cannot satisfy the demand of high-power applications, such as heavy-duty electric vehicles and more electric airplanes.The second issue comes from the fastswitching speed of SiC MOSFETs, where power cables act like transmission lines under steep rising/falling voltages (high dv/dt), with back-and-forth voltage reflections that result in serious overvoltage oscillations at motor terminals.To address these issues, a SiC module-parallel inverter is adopted with elevated current capacity, where the phase voltage is maintained at the midpoint of a coupled inductor connected to the output nodes of each paralleled half-bridge module.By actively controlling the switching delay between the paralleled half-bridge legs, Q3L PWM waveforms are generated at the inverter output nodes that can mitigate the motor overvoltage due to the voltage reflections through power cables.An active current control technique is also proposed to facilitate the current balance between the paralleled half-bridge legs.The proposed Q3L PWM-based module-parallel inverter is experimentally verified using a SiC-based cable-fed motor drive system.The results show that the proposed approach can extend the current capabilities of SiC devices as well as mitigate motor overvoltage, enabling the adoption of SiC devices in high-power motor drives.

I. INTRODUCTION
P OWER density, efficiency, and reliability are key design drivers and central concerns for adjustable speed drives in a range of applications including industrial automation and robotics, transportation, and renewable energy systems.Wide bandgap power semiconductor devices, such as silicon carbide (SiC) MOSFETs, offer significant potential for improving the power density and efficiency of adjustable speed drives due to their superior material characteristics [1], [2], [3], [4].For instance, SiC MOSFETs can operate at higher switching frequencies while maintaining high efficiency due to their fast-switching speed, compared with Si insulated-gate bipolar transistors (IGBTs), which reduces passive filtering components and cooling requirements [5], [6], [7].Consequently, SiC MOSFETs offer a promising alternative to Si IGBTs in adjustable speed drives for a wide range of applications, where they are becoming more competitive in energy saving, power density improvement, and system-level cost reduction [1].
However, the application of SiC MOSFETs in adjustable speed drives is also facing several issues [8], to fully realize their potential [1].Among them, there are two major challenges of adopting SiC MOSFETs in high-power adjustable speed drives, i.e., the maximum output power limitation of the inverters [9] and the serious transient overvoltage at motor terminals [10].
The first challenge is due to the lack of high current rating SiC switching devices [11].With wider electrification in high-power applications, inverters with high-power ratings are necessary.For example, inverters in the power range of 100-500 kW for heavy-duty electric vehicles [12] and megawatts-level power inverters for more/all electric aircraft [13], [14], [15] are highly demanded.Due to the limited current rating of SiC chips, parallel connection of SiC MOSFETs can be an approach to improve the current capacity of switching devices [11].Furthermore, parallel connection of switching devices is also a cost-effective approach even in low-power applications since the high-current devices are generally more expensive than equivalently rated parallel-connected low-current counterparts.For example, at the time of writing, the Wolfspeed C3M0016120D SiC MOS- FET (1200 V/115 A, $70.4) is 37% more expensive than two C3M0032120D (1200 V/62 A, $25.7) low current ones [16].However, paralleling SiC devices is a challenging approach due to the potential current imbalance among paralleled SiC MOSFETs [11].Owing to the unavoidable switching time mismatch and/or characteristic difference among the paralleled devices, both the steady-state and transient currents may not be equally shared among the devices, resulting in overcurrent and overtemperature in some devices [17].This adversely affects the inverter reliability and limits the usable current rating of the devices.Therefore, several approaches have been proposed to overcome the current imbalance among the switching devices [17].For example, Wen et al. [18] used active gate drivers to handle the imbalance current.However, these gate drivers require high-bandwidth current sensors and feedback control, which increases the implementation complexity.Moreover, paralleling multiple chips also poses challenges to the gate driver design, where a very-high current output capability is required to drive the paralleled chips to achieve simultaneous turn-ON and turn-OFF while providing a very fast switching speed [9].
The second challenge comes from the fast voltage transients (high dv/dt) of inverter output voltages due to the fast-switching speed of SiC MOSFETs [10].In a typical SiC cable-fed motor drive system, as shown in Fig. 1, the fast-fronted voltage transients make the power cables act like transmission lines, where the waves travel along the cable forward and backward [10].Due to the characteristic impedance mismatch between the cable and motor, the voltage pulses are reflected at motor terminals, resulting in serious overvoltage, which can double the inverter voltage [19].This is known as the reflected wave phenomenon [20].The resultant overvoltage due to the reflected wave phenomenon depends on the employed cable length, rise and fall times of pulsewidth modulation (PWM) voltage pulses, and characteristic impedances of the cable and motor [21].With shorter switching rise/fall times of SiC MOSFETs, the overvoltage at motor terminals is more common and severe in SiC adjustable speed drives compared with Si counterparts, where the voltage at the motor terminals can be twice the inverter voltage with a few meters of cable [22].In addition to the fast-switching speed, the higher switching frequency of SiC power inverters brings new issues for the adjustable speed drives, i.e., the double pulsing effects, where the motor may experience more than twice the inverter voltage due to the addition of reflected voltage pulses [10].The resultant overvoltage stress at motor terminals  adversely affects the lifetime of motor winding insulation through the inception of partial discharges that progressively yield to the degradation and premature failure of organic coatings of motor coils [23].This significantly affects the reliability and lifetime of adjustable speed drives.
Several approaches have been investigated in literature to attenuate the overvoltage oscillations at motor terminals in cable-fed motor drive systems [21], [22], [24], [25], [26], [27], [28].In [21], the voltage slew rate is actively shaped using a SiC soft-switching inverter, as shown in Fig. 2(a), to mitigate the motor overvoltage and reduce the switching loss.Zhou et al. [22] and Lee and Nam [25] adopted a T-type inverter, as shown in Fig. 2(b), to generate a quasi-three-level (Q3L) voltage waveform to cancel out the motor overvoltage oscillations.Authors in [26], [27], and [28] further developed the Q3L PWM concept by using new circuit topologies.However, these approaches cannot be employed in high-power applications due to the lack of high-current-rating SiC devices.
This article aims to tackle the aforementioned two issues of deploying SiC MOSFETs in high-power adjustable speed drives.The main contributions of this article are summarized as follows: A Q3L PWM-based module-parallel inverter, as shown in Fig. 3, is proposed to elevate the current capacity and mitigate the motor overvoltage in SiC-based adjustable speed drives.The motor overvoltage mitigation mechanism of the proposed PWM scheme is mathematically derived in both time and frequency domains.In addition, to facilitate the current balance between the parallel-connected modules, an active current control technique is proposed.
The rest of this article is structured as follows.Section II provides brief modeling of the voltage reflection phenomenon in adjustable speed drives and analyses the Q3L overvoltage mitigation mechanism in the time domain and frequency domain.In Section III, the proposed Q3L PWM-based module-parallel inverter is presented and its operation principles are illustrated.Section IV provides experimental verification of the proposed approach.Finally, Section V concludes this article.

A. Modeling of Reflected Wave Phenomenon
In SiC adjustable speed drives, the fast-switching PWM pulses are reflected at the motor terminals due to the impedance mismatch between the power cable and motor, resulting in excessive motor overvoltage oscillations.Several models have been presented in the literature to investigate the reflected wave phenomenon.For example, Zhou et al. [21] used a bounce diagram to graphically illustrate the voltage reflection mechanism.Fig. 4 depicts the inverter voltage V s and motor terminal voltage V m in a cable-fed motor drive system, where V dc is the dc-link voltage, t p is the wave propagation time in the power cable from one end to the other, Γ m and Γs are the reflection coefficients at the motor and inverter terminals, respectively.
Referring to Fig. 4, the maximum overvoltage at the motor terminals can be given as [21] V where Γ m is calculated in terms of the characteristic impedance of cable Z c and motor Z m as [21] Γ Typically, Z m Z c , which results in Γ m = 1, implying the voltage is fully reflected at the motor side.
The overvoltage oscillation frequency f rw can be expressed as [21] where the propagation time t p depends on the adopted cable length l c and the per-unit length inductance L c and capacitance C c as [21]

B. Q3L Overvoltage Mitigation Mechanism in Time Domain
If the inverter output voltage V s is reshaped as a Q3L waveform, where the rising edge is split into two identical voltage steps (V s1 and V s2 ) with a proper dwell time t dwell , the motor overvoltage can be significantly attenuated, as shown in Fig. 5.The amplitudes of V s1 and V s2 are V dc 2 .V s is given by ( Referring to Fig. 5, the two voltage steps V s1 and V s2 experience voltage reflections while traveling from the inverter to the motor across the cable due to the impedance mismatch between the cable and the motor.Note that the reflection coefficients at the inverter and motor sides are assumed to be unity.V m1 and V m2 are the reflected voltages of V s1 and V s2 , where they both have an amplitude of V dc .Accordingly, the resultant motor voltage V m can be given as If V s2 lags V s1 by t dwell = 2t p , the overvoltage oscillations of V m1 and V m2 can be fully counterbalanced, as shown in Fig. 5. Thus, the motor overvoltage can be significantly mitigated.
In a similar mitigation mechanism, if the falling edges are shaped as a Q3L waveform with a dwell time t dwell = 2t p , the motor will not experience overvoltage oscillations at the falling switching transitions either.

C. Q3L Overvoltage Mitigation Mechanism in Frequency Domain
The Q3L overvoltage mitigation approach can be further analyzed in the frequency domain.Since Q3L voltage V s is composed of two identical voltage steps V s1 and V s2 with an intermediate dwell time, the inverter output voltage V s can be represented by the pulse train shown in Fig. 6.
Referring to Fig. 6, A/2 is the pulse voltage amplitude, τ is the average pulsewidth measured at half the pulse amplitude, T is the fundamental cycle time, and t r and t f are the pulse rise and fall times, respectively.For simplicity, the waveform is assumed to be symmetrical (i.e., t r = t f ) with a constant duty ratio (d = τ /T ).
According to Fourier analysis, the pulse train V s1 shown in Fig. 6 can be expressed as [29] V where ω is the angular frequency of the waveform and c n1 is the Fourier series coefficient given as Since V s2 lags V s1 by t dwell , the Fourier series expansion of V s2 can be expressed as Substituting ( 8) and ( 9) into (5), the Fourier series expression of V s is where c n is the Fourier series coefficient given as 1 + e jnωt dwell .(11) At the antiresonance frequency of the motor drive system (i.e., ω = 2πf rw ), the Fourier series coefficient is From ( 12), it can be derived that when t dwell = 1 2f rw = 2t p , c n = 0, that is, the motor overvoltage can be ideally eliminated since the voltage component exciting the resonance is zero.

III. Q3L PWM FOR MODULE-PARALLEL INVERTER
The Q3L voltage pulse train shown in Fig. 6 can be generated using the module-parallel power inverter by actively controlling the switching delay between the paralleled modules.

A. Module-Parallel Power Inverter
Referring to the circuit schematic shown in Fig. 3, each phase of the module-parallel power inverter consists of two half-bridge-legs connected using two identical inductors.This inverter can be further extended to multi-leg paralleled inverters depending on the switching devices' current rating and the required power level.For simplicity, the two half-bridge-leg paralleled inverter shown in Fig. 3 is considered in this article.Note that the inductors can be either coupled or uncoupled.The coupled inductor with self-inductance L is employed herein because it can significantly reduce the core loss and size, compared with the uncoupled one.

B. Implementation of Q3L PWM
Referring to Fig. 3, the inverter output voltage V XN (X = A, B, or C) is pertinent to the output voltages of half-bridge legs X 1 and X 2 (V X1N and V X2N ), as Accordingly, the Q3L PWM voltage can be obtained by inserting a time shift t dwell between the output voltages of the paralleled legs (X 1 and X 2 ).Fig. 7 illustrates the gate signal generation for the switching devices in phase A, where the reference modulation signal u ref is compared with two identical triangular carrier signals but shifted by t dwell .Fig. 8 describes the detailed switching transitions considering the devices' parasitic elements when the output current is positive, where Fig. 8(a)-(e) illustrates the commutation process of the output voltage when rising from 0 to V dc , whereas Fig. 8(f)-(j) illustrates the commutation process of the output voltage when falling from V dc to 0. The corresponding voltage and current waveforms for these commutation processes are shown in Fig. 9.The phase current i A is assumed to be equally split among the paralleled legs (A 1 and A 2 ) when the commutation starts.
It is worth noting that for a single half-bridge-leg, the commutation process for the output voltage traversing from 0 to V dc is governed by the gate resistance of the adopted gate driver, Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.whereas the commutation process of the output voltage from V dc to 0 is governed by the load current and parasitic elements [30].Referring to Fig. 8(a)-(c), the output voltage V A1N swings from zero to V dc when the turn-ON gate signal is applied to the top switch S a1 at t 2 .Therefore, the output voltage V A1N is denoted by the steep rising edge, as shown in Fig. 9.According to (13), the inverter output voltage V AN becomes V dc /2 with halved voltage slew rate.Meanwhile, the inductor currents i La1 and i La2 start to increase and decrease, respectively, with the same current slew rate, as The same commutation processes are applicable to the halfbridge-leg A 2 , as shown in Fig. 8(d) and (e).The output voltage V A2N starts to increase from 0 to V dc when the turn-ON signal is applied to S a3 at t 5 , as shown in Figs.8(d) and 9.According to (13), the inverter output voltage V AN traverses from V dc /2 to V dc , as shown in Fig. 9.Then, the inductor current keeps fixed since the voltage across the inductors is zero.The duration of the intermediate voltage level of the inverter output voltage V AN depends on the time delay between the gate signals for legs A 1 and A 2 .Referring to Fig. 9, the current difference between the half-bridge legs is denoted as the offset current I offset as Fig. 8(f) and (h) shows the commutation process for leg A 1 from the top switch to the bottom switch.Since the commutation is affected by the load current and parasitic elements of the devices, the voltage V A1N tardily decreases in a linear manner within a falling time t fall , as shown in Fig. 9. t fall is given by [30] t fall = 2C oss V dc i load (16) where C oss is the output capacitance of SiC MOSFETs.
The output voltage V A1N keeps V dc /2 after the current fully traverses to the bottom switch S a2 .Meanwhile, the inductor current i La1 decreases and i La2 increases, respectively, with the same current slew rate as (14).After a dwell time t dwell , the same commutation processes are applied to leg A 2 , resulting in the output voltage traversing from V dc /2 to zero, as shown in Fig. 8(i) and (j).After that, the inverter outputs zero voltage and the currents flow through the coupled inductor resume the same again, as shown in Fig. 9.

C. Active Current Balance Control Approach
Referring to Fig. 9, the current flows through leg A 1 is higher than that of leg A 2 during the switching transient, resulting in higher power loss and temperature rise in leg A 1 than A 2 .Besides, due to the inevitable mismatch among the devices' characteristics, the current flowing through the two half-bridge legs would be unequal at the steady state, resulting in different steady-state loss and temperature rise among the legs.The above issues would result in inductor core saturation and thermal unbalance among the switching devices reducing the usable current rating of the devices.Therefore, the current sharing among the bridge legs should be actively controlled.
The flowchart in Fig. 10 outlines the proposed active current balance approach for phase A, which involves measuring the inductor currents i LA1 and i LA2 , and accordingly determines which bridge leg is triggered first during switching.For example, if i LA1 > i LA2 , the bridge-leg A2 will be switched first, otherwise, bridge-leg A1 will be switched first.As the sample and update frequencies are equal to the switching frequency, the currents for each bridge leg can be actively balanced at the switching frequency.With this approach, the switching devices in the bridge legs will have equal rms current value, resulting in the same temperatures.

D. Impact of Inductance and Cable Length on the Offset Current Among Bridge Legs
Fig. 11 shows the offset current I offset with respect to the coupled inductance at different cable lengths, where the dc link is 400 V and the wave propagation time is assumed to be 5.22 ns per cable meter [31].The dwell time is changed according to the employed cable length.Referring to Fig. 11, the offset current increases with the cable length but decreases with the employed coupled inductance, which can be explained using (15).

E. Impact of Duty Cycle
Referring to Fig. 7, the module-parallel inverter can generate the Q3L PWM voltage waveform under normal conditions, which can effectively mitigate the overvoltage at motor terminals in cable-fed motor drives.Under very low duty cycle modulation, as shown in Fig. 12, the inverter generates two consecutive voltage pulses separated by t dwell , with amplitudes of V dc /2.Even when the motor is supplied by these voltage waveforms, the maximum voltage at the motor terminals remains within 2 * V dc /2 = V dc , i.e., twice the incident voltage.Therefore, the proposed approach can effectively mitigate motor terminal overvoltage under both normal and low duty cycles, i.e., the proposed approach has no minimum duty cycle limitation.

IV. EXPERIMENTAL RESULTS
To verify the proposed approach, a three-phase moduleparallel power inverter based on SiC MOSFETs is built to supply a Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.three-phase induction motor through 12.5 m, four core, 13 AWG long cable, as shown in Fig. 13.Three coupled inductors with 15 μH self-inductance are employed.Note that to reduce the core loss and keep the same inductance among the bridge legs, the coupled inductor with a bifilar winding structure is used.Fig. 14 shows the schematic and photo of the employed coupled inductor.The SiC power inverter is controlled the Q3L PWM scheme with t dwell = 2t p .Note that the wave propagation time t p can be obtained using the offline methods presented in [21].Table I shows the main parameters of the experimental setup.
Fig. 15(a) and (b) shows the schematic and photo of the current measurement circuit for phase A. As shown, the differential current of legs A 1 and A 2 is measured using one current sensor, where the obtained differential current is fed into the control  board for the active current balance control.This current measurement approach can reduce the number of current sensors      from six to three for the three-phase module-parallel power inverter.
Fig. 16 shows the inverter line voltage V s , the corresponding voltage at motor terminals V m , and the inverter output phase current for the motor startup experiment, where Fig. 16  respectively.As can be noticed in Fig. 16(a), a significant overvoltage at the motor terminals, which is about 2.0 p.u., exists across the motor terminals when the motor is supplied by the conventional 2L inverter.In contrast, the motor overvoltage is significantly mitigated when the proposed Q3L scheme is used, where the peak voltage is about 1.2 p.u., as shown in Fig. 16(b).In addition, there are high-frequency spikes in the inverter output current for the 2L inverter.These high-frequency harmonics of the current are due to the high dv/dt charging and discharging of the cable parasitic capacitance, along with voltage reflections across the cable.In contrast, the module parallel power converter has cleaner output current waveform than that of the 2L inverter.This returns to the overvoltage mitigation ability of the proposed module-parallel inverter in addition to the attenuated dv/dt of its output voltage which is half that of the 2L inverter.This effectively suppresses the high-frequency current spikes.
Fig. 17 shows the experimental results for steady-state operation of the motor where Fig. 17(a) and (b) shows the results when the motor is supplied by a 2L converter and the moduleparallel inverter, respectively.The results demonstrate that the module-parallel inverter effectively reduces overvoltage at the motor terminals and has a cleaner output current waveform compared to the 2L inverter.In addition, the proposed modulation scheme has a minor impact on the dc-link capacitor's current ripple, given that the dwell time is typically in the nano-to micro-second range.This is demonstrated in Fig. 17, where the dc-link current ripple is 1.8A and 2.0 A for the 2L inverter and the module-parallel inverter, respectively.Fig. 18 shows a comparison between the 2L converter and the module-parallel power inverter in terms of their current frequency response, where Fig. 18(a) and (b) shows the frequency spectrum and THD of the inverter output current, respectively.The results show that the module-parallel inverter effectively reduces high-frequency harmonics and achieves a lower THD than the 2L inverter.
Fig. 19 shows the experimental results when the motor is supplied by the 2L inverters, where Fig. 19(a) shows the results for one switching cycle, whereas Fig. 19(b) and (c) shows the zoomed-in results, respectively.Referring to Fig. 19, the voltage at the motor terminals oscillates in a damped manner with magnitudes of 1.9 p.u. and 1.8 p.u. at the rising and falling edges, respectively.
Fig. 20 shows the experimental results when the motor is supplied by the Q3L PWM-based module-parallel power inverter, where Fig. 20(a)-(c) shows inverter and motor line voltages for at the switching cycle and the rising and falling edges, respectively.Compared with the experimental results of the 2L inverter, the motor overvoltage is significantly attenuated, where the peak voltage is about 1.25 p.u., when the module-parallel inverter is employed, as shown in Fig. 20.This is because the module-parallel inverter can generate the Q3L voltage waveform at both the rising and falling edges, as shown in Fig. 20(b) and (c).
Fig. 21(a) and (b) further shows the module-parallel inverter bridge-leg output voltages V A1N and V A2N , and the inverter output voltage V AN for the rising and falling edges, respectively.As can be noticed, while each bridge-leg generates a 2L voltage, the inverter generates a Q3L voltage, which can be used to mitigate the motor overvoltage due to the reflected wave phenomenon.In addition, the inverter output dv/dt of the module-parallel inverter is half of the output voltage of each phase-legs, as shown in Fig. 21.
Fig. 22 shows the inverter bridge-leg currents I A1 and I A2 , the inverter phase current I A , and the inverter output voltage V A for phase A, where Fig. 22(a) and (b) shows the results of the inverter without and with using the active current balance control approach, respectively.Referring to Fig. 22(a), there is a constant offset current, which is about 2 A for the two legs, when the active current balance control is not used.By contrast, the bridge-leg current can be balanced when the active current balance control approach is employed, as shown in Fig. 22(b).
Fig. 23 compares the efficiency of the 2L inverter and the Q3L module-parallel inverter at different power based on the PLECS power loss simulation.The results indicate that the 2L inverter is slightly more efficient than the Q3L module-parallel inverter, with an efficiency that is about 0.5% higher.

V. CONCLUSION
This article proposed a Q3L PWM-based module-parallel inverter to elevate the power capacity and combat the motor  overvoltage when using SiC MOSFETs in high-power adjustable speed drives.The module-parallel power inverter could extend the output current capacity of the inverter because the load current could be evenly distributed among the bridge legs.The proposed approach could generate a Q3L output voltage to Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.mitigate the motor overvoltage.The general idea of the overvoltage mitigation mechanism was derived from the time domain and frequency domain.The theoretical analysis showed that by actively shifting the gate signal of one bridge leg before the other bridge leg by t dwell , it can mitigate the motor overvoltage significantly.The effectiveness of the Q3L PWM was experimentally verified with the SiC bridge-leg parallel inverter-fed drives.The experimental results showed that the proposed scheme could significantly mitigate the motor overvoltage, compared with the conventional 2L inverter.

Fig. 4 .
Fig. 4. Inverter voltage V s and motor terminal voltage V m in cable-fed motor drive system.

Fig. 5 .
Fig. 5. Overvoltage mitigation mechanism when the voltage is shaped as a Q3L.

Fig. 9 .
Fig. 9. Gate signals, the output voltages, currents for bridge legs (A1 and A2), and the inverter output voltage during switching transitions.

Fig. 11 .
Fig. 11.Offset current with respect to the inductance and cable length when the dc-link voltage is 400 V in the Q3L PWM-based moduleparallel inverter.

Fig. 12 .
Fig. 12.Output voltage the module-parallel inverter under a very low modulation index.

Fig. 14 .
Fig. 14.(a) Schematic and (b) photo of the coupled inductor using the bifilar winding pattern.

Fig. 15 .
Fig. 15.(a) Schematic and (b) photo of the current measurement for one phase.

Fig. 16 .
Fig. 16.Experimental waveforms of inverter line voltage V s and the motor terminal voltage V m for motor startup experiment when the motor is supplied by (a) 2L inverter and (b) module-parallel inverter.
(a) and (b) shows the results when the motor is supplied by a two-level (2L) converter and the proposed Q3L module-parallel inverter, Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

Fig. 17 .
Fig. 17.Experimental waveforms of inverter line voltage V s and the motor terminal voltage V m , the inverter output current I phase , and dccurrent I dc for the steady state when the motor is supplied by (a) 2L inverter and (b) module-parallel inverter.

Fig. 19 .
Fig. 19.Experimental waveforms of inverter line voltage V s and the motor terminal voltage V m when the motor is supplied by the 2L inverter for one switching view, (b) extended view at rising edge, and (c) extended view at the falling edge.

Fig. 20 .
Fig. 20.Experimental waveforms of inverter line voltage V s and the motor terminal voltage V m when the motor is supplied by the Q3L module-parallel inverter for (a) one switching view, (b) extended view at the rising edge, and (c) extended view at the falling edge.

Fig. 21 .
Fig. 21.Leg A1 output voltage V A1N , leg A2 output voltage V A2N , and phase A output voltage V AN of the Q3L PWM-based module-parallel inverter.

Fig. 22 .
Fig. 22. Currents of bridge-leg A1 I A1 , bridge-leg A1 I A1 , bridge-leg A1 I A1 for the inverter (a) without and (b) with using active current balance control approach.
Inverter With Paralleled Modules to Extend Current Capacity and Combat Motor Overvoltage in SiC-Based Adjustable Speed Drives Wenzhi Zhou , Member, IEEE, Mohamed Diab , Senior Member, IEEE, Xibo Yuan , Senior Member, IEEE, Lihong Xie , Jun Wang , Member, IEEE, and Zhaobo Zhang