A Comparison of Register Transfer Languages for Describing Computers and Digital Systems

Different notations have been proposed over the years to describe register transfer (RT) systems. They have met with varying degrees of success and to provide a direct comparison of them is a difficult task. One of the reasons for this is the different views of the RT level of design held by the proponents of the languages.


I. INTRODUCTION
LTHOUGH the register transfer (RT) level is a perfectly valid level of design, it has not been fully defined and understood (it is not a problem of youthfulness, the level was recognized as such in the early 50's).As a consequence we do not have a proven and accepted (complete?)set of primnitive elements.Also, there is no accepted design form/style, and usually informal flow- chart and data path diagrams are used.The result is that a designer, working at the RT level must occasionally descend one level (to the gate level) to describe precisely a particular piece of hardware.Contrast this with the gate level of design, with the traditionally accepted set of primitives (AND, OR, FLIP-FLOP, etc.) where it is indeed rare for a designer to have to describe a gate in terms of diodes or transistors (the circuit level).
RT languages are similar to most programming lan- guages since both carry out register assignments.The special nature of hardware suggests that it could be useful to have a special notation, even though programming languages such as Fortran can be used for this purpose.
The need for such a notation is due to the influence that it has upon the designer, simultaneously limiting his intellect (a system may be more easily described in one language than in another) and enhancing it (a notation provides a formal mechanism to generate and transmit knowledge).The main motivation, is that: "Complexity diminishes and clarity increases to a marked degree if algorithms are described in a language in which appropriate control structures are primitive or easily expressible [R06]."1 The fundamental properties of hardwvare systems dictate the properties an RT language must possess.In hardware systems many activities occur concurrently.Thus, it is im- portant to have a natural way of describing parallelism.Other characteristics of hardware systems are the nonrecursive nature of their operation, and the presence of timing issues that must be considered.Since machines are designed from logically disjoint functional units,2 we need ways to describe interactions between units, both as subroutines (hierarchical relationships) and as coroutines (symmetric relationships).The behavior of the system is described by sequences of actions or activities, (where control flows along selected paths-an abstraction), and we need mechanisms to guarantee the harmonious cooperation (synchronization) between activities.
Control operations in the language should provide only the information necessary to understand the behavior of the system and should imply the actual implementation as little as possible.The efficiency of a RT language depends upon the generality of the control operations, i.e., whether a given operation exists as a primitive in an RT set or is described as a composition of more primitive operations.This paper explores the existing RT languages and presents a comparison based on four languages.They were selected on the basis of their characteristics as representa- tive of a class of languages.The languages selected are: ]Fisher's dissertationl [R06] investigates the control structure of programming languages, i.e., the sequencing and interpretation rules for programs.The similarity between RT systems and soft- ware programs makes his study pertinent to the theory of RT systems design.CDL, APDL, APL, and ISP.The comparison is performed by defining a common ground, or kernel, for the entities the languages try to describe.Sections I and II present the levels of digital systems design and the languages selected for this study.Section III presents a characterization of the RT level with the definition of the concepts of carriers and operators at the switching circuit level of design and the generalization of these entities at the RT level.The appearance of control as an explicit entity at the RT level is reflected in the different types of conditional statements in the languages.Section IV deals with the different ways in which concurrent and sequential activities can be denoted.Section V discusses the ability of the languages to denote the behavior of systems built out of a particular set of asynchronous control modules.Section VI deals with their usefulness to describe complex systems (e.g., instruc- tion set processors) and the way a description can be organized to provide different levels of detail.A few re- marks are made, in Section VII, about the implementation of the RT languages for simulation and automatic design purposes.Section VIII defines a set of requirements for writing behavioral and structural descriptions of digital systems.This section also compares the languages selected against the required properties.
II.THE DESIGN LEVELS Five major levels exist in the digital systems hierarchy [R02], for wvhich we are interested in formally defining, using notations, and computer recognized languages.They are as follows.
PMS Level (system level): The top level of description, evaluates the gross properties of the computer system.Its elements are processors, memories, switches, peripheral units, etc, and the parameters are costs, memory ca- pacities, information flow rates, power, etc.
Programming level: The basic components are the interpretation cycle, the machine instructions, and operations (which are defined at the RT level).The behavior of the processor is determined by the nature and sequence of its operations.This sequence is given by a set of bits in primary memory (a program) and a set of interpretation rules.Thus, if we specify the nature of the operations and the rules of interpretation, the actual behavior of the processor depends solely on the initial conditions and the particular program.
Register Transfer Level (functional level): Data flow and control operate in discrete steps.A combination of switch- ing circuits is used to form registers, register-transfers, and other data operations.The elements (registers) are com- bined (transformed) according to some rule and then stored (transfered) into another register.The rules of transformation can be almost anything, from simple transfers to complex logical and arithmetic expressions.Switching Circuit Level (sequential and combinational sublevels): The system structure is given by a collection of gates and flip-flops, and the behavior by a set of Boolean equations.Timing is carried out at a finer degree than at the preceding level, a time unit being usually on the order of a gate delay.
Circuit Level: Gates are described as some interconnection of diodes, transistors, resistors, etc. according to electrical circuit laws.Most of the discrete properties of the previous two levels are lost, and timing is carried out at a finer degree, where transient behavior is an important consideration.
Part of the characterization of a system level, (as described above) is the existence of a notation for repre- senting the system, that is, the components, modes of combination, and laws of behavior.The three intermediate hardware levels: programming, register transfer, and switching can all be described using a single language.In fact, conventional programming languages have been used.The issue is, however, how much they must be changed to reflect parallelism, timing and the structure of the object being represented.

III. THE LANGUAGES
Four languages were selected on the basis of their char- acteristics as representative of a class of Register Transfer Languages.They, are as follows.
1) CDL [LO6], [L07]: One of the most successful, it has been in use for several years and has been implemented for simulation and design automation purposes [S12].
CDL is an excellent representative of the class of nonpro- cedural languages (the distinction is given below).
3) APL EL16], [L17]: Selected because of the richness of the set of data operators and its facility to handle arrays.A major drawback is the lack of facilities to describe parallel activities.It is used in the Alert System [S05], [S06] developed at IBM as a front end for the design and logic automation systems ES04], [S18].
4) ISP ER02], [L04]: Developed initially to describe the primitives of the programming level of design, handles concurrency, and sequencing of activities in a simple fashion and provides an adequate set of data and control operators.
Nonprocedural languages [L01], [L05], [L06], [L09], [L22], [L24] attach no meaning to the lexicographical ordering of statements describing the operation of the sys- tem.Statements are associated with some sort of "label" describing the condition for execution (activation) of the operation described by the statement(s).They can be written as a table, where each entry consists of a lable (activation conditions) and a set of activities.
Procedural languages impose an explicit ordering in the activities, given by the sequential ordering of the state- ments.The activation of activities is conditioned by the completion of the preceding ones.Concurrent activities are described in "time blocks" and the descritption is then a list of these blocks.
BARBACCI: REGISTEIR TRANSFER LANGUAGES IV.CHARACTERIZATION OF THE RT LEVEL The RT level is a generalization of the swvitching circuit level.The structural elements are arrays of identical sub- systems belonging to the Switching level, i.e., registers are made of flip-flops and gates, driven by clocks (or clock- like signals).The behavior is described by transformations (functions) and transfers between registers.The key element that sets this level apart from the lower level is the appearance of control (the ability to perform these trans- formations and transfers in a selective way) as an explicit entity.Section III-A describes the primitive components at the Switching Circuit level.The generalization of these components at the RT level is presented in Section III-B.

A. Carriers and Operators
Operators are entities that produce information by trans- formation of bit patterns to which a meaning has been assigned.These bit patterns reside in carriers, which are the entities used in storing and transmitting the informa- tion to and from the operators.
Operators take their input from carriers, perform their function on the data and present their outputs onto car- riers.At the switching circuit level, operators range in complexity from simple transfer paths between carriers, to logical gates, to combinational networks.
Carriers can be divided into two types, according to the latency of the information stored in them.Thus, we have memory components where the information stored in them is kept over periods of time; and we have memoryless carriers, where the information is of a more transient nature.An example of the latter is wires coming out of a combinational network.
It is not possible to make a clear distinction between these two types of carriers on the basis of their function in transmitting or storing information.There are many cases in which the distinction is rather foggy.For instance, a bus is used to transmit information, i.e., a carrier, but it also keeps it (a memory function) for a period of time adequate for the information to be collected at the receiving end.On the other hand, a set of flip-flops connected as a shift register provides both a storage and transmission function.
Among the physical operators and carriers we have the individual gates (AND, OR, NOT, EXOR, EQUIV, NAND, NOR, etc.) and flip-flops of different types (RS, JK, D, etc.).These operators and carriers can be combined to form combinational and sequential networks.
At the switching level, notations are based on Boolean equations or logic diagrams and there seems to be general acceptance of the industrial or military standards cur- rently in use.The use of logic equations allows a more concise representation of the system but does not provide for physical configuration descriptions.Logic diagrams provide a pictorial representation and allow the description elements required by the circuits (physical restrictions) but not by the logic.(2) Indexing is from 0 to N-I or I to N depending on system parameter.
(3) Memory declarations require explicit use of memory address register.
(4) Numbers represent element names and not relative positions (as subscripts) along a given dimension.
(5) Mnemonic subscripts can be used to represent ranges of subscripts.Does, not allow independent naming of subregisters.
(6) Up to two dimensions in ALERT.
(7) Macros are used for this purpose in ALERT.

B. Arrays
The first specialization introduced by the RT level is the generalization of the operators and carriers, i.e., arrays of (identical) operators performing simultaneously on the information held in arrays of (identical) carriers.At this point, carriers become hierarchically organized informa- tion structures, in which each level consists of a number of subearriers, all identically organized.This decomposition eventually yields elementary carriers that-can not be de- composed further (bit carriers).
This abstraction allows the designer to reduce the com- plexity of his task by using logic equations to describe the network (logic diagrams are less useful since the objective is the reduction of detail, specially when logically irrele- vant).This implies that operators and operands are now actually arrays of identical entities.Subearriers are re- ferred to by some subscripting or array notation (similar to those in most programming languages).A concatenation operator is used to represent compound carriers.RT languages usually have the following elements (see Table I): Registers are vectors of components whose values can be characters from an arbitrary alphabet.They are declared by giving the name of the register, the dimensions, and the size of the alphabet (defaulted to 2 in most cases, i.e., bits).Dimensions are given in brackets or parenthesis, as a list of subscripts or element names.Abbreviated lists are (1) Total register access by name alone.
(2) Only for constant subscripts in ALERT.
(3) Always requires use of the Memory Address Register used in the declaration.
(4) Only for single bit access in ALERT.
$ubregisters are part of registers and are usually de- clared with their own name and subscript specifications.
Compound registers, formed by concatenation of several registers and subregisters can be declared.The declaration usually provides a name and subscript specifications.
Arrays of registers are declared by providing a name, dimensions, and the specification of the individual registers (element names and base).
Carriers are accessed through their names and the specification of the subcomponents by some subscripting mechanism (see Table II).There are several modes of specifying this subscripting, depending on the number of dimensions and the number of subcomponents accessed.The following are typical RT language properties: Single characters (for instance, bits) are accessed by providing a full set of subscripts, one for each dimension up to the individual character.
Full registers are accessed by their names alone (defaulting the list of individual component names and bound pairs).Register arrays require specification of the sub- scripts up to the individual register.
Scattered (partial) registers and memories are specified by providing a list of component names and bound pairs, in the order in which access is desired (not necessarily the order they occupy in the declaration).
Multiple registers can be specified by lists of com- ponent names and bound pairs along the dimensions of the register array.
The primitive operators (see Table III) are classified into logical, arithmetic, vector, and special.The symbols used to represent the operators are either special charac- ters or combinations of letters (names).
Expressions are formed by combination of constants, operators, and operands.Rules of precedence are usually as in Algol, with the notable exception of APL (right to (1) Since the registers can have elements in any base, the logical operators have been generalized in APDL and ISP, to handle non binary values.
(2) Operators that modify dimensions of variables are excluded in ALERT.
(3) Expressions can be followed by a modifier, providing more information about the meaning and interpretation of the operands and operators.A modifier consists of a data type specification or an operation mode enclosed in curly brackets, e.g.: 8*2 {shift left} (4) Special operators, (-SET and +-RESET, are used in ALERT to select the SET and RESET inputs to the flip-flops. eft precedence).The value of the expression represents the signals at the output of the combinational network that performs the operation.New operators, beyond those of the Switching level, are introduced such as a transfer (+-) operator to describe the loading of information in a register.Several complex operations are now taken as primitives, for instance, shift and rotation.

C. Conditional Actions
At the switching circuit level the systems are considered as networks of elements performing their activities continuously.All components are considered equally relevant to the specification of the system state.When the system is of more than trivial size, the difficulty in comprehending the behavior increases, and new abstractions are intro- duced.
In RT level descriptions, the elements are assumed to be going through periods of activity and rest.Clearly, the physical elements are always active.The abstraction merely consists in specifying, at different times, the com- ponents where "interesting" activities are taking place.For instance, storing new information in a carrier or changing the inputs to an operator.
This abstraction is reflected in the description by the use of conditional operators that specify the subsystems that are to be considered "active" (in this new, abstract sense), and also the conditions for this transition of activity state to take place (see Table IV).
Conditional statements are used to select actions under a condition generated by a test network.The network is described by a Boolean or relational expression.Single bit tests are usually simplified by using the bit itself as a Boolean expression.This can be extended to a zero/nonzero test for a whole register.
Conditional statements, in most languages, can be nested to any depth (in APL, conditional statements are implemented by testing and branching).
V. CONCURRENT AND SEQUENTIAL ACTIONS At the switching circuit level, logic equations describe the nature of the input signals to the individual flip-flops, including the timing and control pulses.
In RT level descriptions, the basic building blocks are the simple actions, for instance, the transfer to a register of the contents of another register or the value encoded in the output lines of a combinational network.Simple actions can be executed in parallel if there is no conflict in the use of resources (e.g., simultaneous transfers to the same register, or simultaneous use of a bus to transmit different pieces of information).
An accurate description of a hardware system must specify the time required to perform the operations, usually in terms of a basic cycle time or time unit.Time blocks are used to group actions that are performed concurrently (taking a certain number of time units to complete).A succession of time blocks may be used to define sequential operations.The selective activation of components, intro- duced in the previous section, allows the representation of the timing and control signals as the condition for the activation of the transfer operation (represented as an assignment statement).The data (logically relevant) part of the original equations forms the expression whose "value" is transferred to the register.
At the RT level, concurrent activities are described by allowing them to be activated simultaneously (i.e., under the same conditions).Synchronous or asynchronous sys- tems differ mostly in the way the activation conditions are specified, i.e., whether it is a signal coming from a central clock or a signal produced at the completion of the pre- ceding activities or a combination of both.3 The concept of selective activation of elements in the system introduces the first classification of RT languages into procedural and nonprocedural languages.
A. Sequencing in Nonprocedural Languages Nonprocedural RT languages use some special control variables to form a label describing the conditions for exe- cution of a time block.Sequencing (see Table V) is per- formed by modifying the control variables used in the labels; hence, enabling or inhibiting the activation of the time blocks.The modification of these control variables can be made explicit, as part of the operations performed Clocks are special units used to generate sequences of pulses that can be used to step the actions of the system.Clock variables when used in expressions are considered as Boolean variables whose value alternates between 0 and 1 automatically, according to some frequency.Synchronous systems operate in synchronism with the clock pulses, and the length of the time blocks is usually the period of the clock.Asynchronous systems do not usually require a clock.Each time block can take different time intervals, depending on the operations performed.(I) The branch operator -e is used to select a label or line number.The right hand side evaluates to a vector and the branching is to the line number given by the first element of the vector.The next line is taken if the vector is empty.The ALERT (simplified) syntax is: IF ( Boolean expression -) GO TO label.
(2) Corresponds to the IF ... THEN ...; case of Algol: Boolean expression X actions (1 ) Used with other variables in control expressions.
(2) Used to step the operations inside a block defined by a state label, thus providing a hierarchy of time blocks.
in the time block or can be generated by an independent entity of the system, working concurrently, for instance a clock or a finite state automation.
Some languages, like Cassandre [LO1] and DDL [L09], make use of finite state machines as the controlling entities for the operations.They use state registers to store infor- mation about the state of the system.Special operators are used to describe the sequencing of operations by testing and modifying the value, i.e., the state held in the state registers.

B. Sequencing in Procedural Languages
In procedural RT languages, systems are described as lists of statements representing the actions.Parallel actions are grouped into time blocks and sequential actions are described as lists of time blocks (see Table VI).Some- times this definition can be used recursively (by using some type of brackets), to build complex time blocks (a group of concurrent sequences).
Conditional activities can be of two types, depending on the interpretation of the test.In some cases, the test is continuously performed and the actions are initiated every time the condition becomes true, i.e., there is a monitoring function being performed concurrently with the rest of the activities.In other cases, the test is performed once, and the actions are executed or skipped depending on the result.
Time blocks are described as a list of conditional and (1) List of time blocks separated by `;".
(2) List of actions using the term "next" as delimiter.
(3) Concurrent actions are described in time blocks of the form: n TIME BEGIN .... .END to describe a statement or group of statements requiring n cycle times.
(4) ALERT provides some conventions to describe concurrent activities.
(5) In ISP concurrency of actions is assumed by default.Concurrent actions are described as a list of statements using the ";" as delimiter.
(6) Time blocks can not be nested.IF EVER statements are taken as declarations, local to an Algol block and can be nested to any depth.(7) Parenthesis are used to nest statements and to indicate the scope of conditional activities.Complex sequential and concurrent activities are described using ";", "next", "'" aind ")" in a block structured way.(8) Pulses are Boolean variables that are automatically reset to 0 one cycle time after they are set to 1. unconditional actions.All nonmonitoring statements are executed once and in the order in which they are written (unless modified by branches).Monitoring statements are assumed to be permanently active and performing the test.They cease to be active when the end of the time block is reached (the scope of a monitoring statement is that of the time block in which it occurs).
Delay operators are used to stop the execution of a sequence for a number of time units.Delays are similar to an empty time block that takes the appropriate number of time units.
Since APL does not allow the description of concurrent activities, Alert provides several conventions to that effect.
Concurrency of simple actions can be determined auto- matically by the system.The algorithms used will try to group the sequence of simple actions into the minimum number of time blocks.For each sequence of time blocks obtained in this fashion, a, sequence counter is provided to step the machine through the time blocks.Sequencing is obtained by stepping the counter, by forcing a value into it, or inhibiting the counting when waiting for a condition to become true.At a higher level, concurrency is obtained by dividing the description into microprograms capable of operating concurrently.Each microprogram specifies whether the system is to provide the grouping of simple actions or not.In the latter case the statements are assumed to be active simultaneously (as in nonprocedural languages, with the enabling and disabling of actions explicitly described in the microprogram).

VI. ASYNCHRONOUS CONTROL PRIMITIVES
AND THEIR REPRESENTATION The Computation Structures Group at MIT is involved in the investigation of formal descriptions of computer systems.In particular the definition of asynchronous con- trol structures [M07], generating signals to direct the actions of data operators in a data flow structure.
Nine types of control modules were identified [Mll] as sufficient to implement simple control structures.The modules are interconnected by direct links that are capable of transmitting ready and acknowledge signals used to indicate a request for some operation or the completion of a requested action, respectively.The reasons behind the selection of this particular set of modules, their represen- tation in terms of Petri-nets, and other formal considera- tions, do not belong in this paper.Our concern lies on the presence or absence of facilities to implement similar control function as primitives in the RT languages.The nine modules are: 1) The source module generates a ready signal each time an acknowledge signal is received.
2) The sink module responds with an acknowledge each time a ready signal is received.
3) The sequence module causes ready/acknowledge cycles to occur on each of its output links, one at a time, for each ready signal received on the input link.
4) The wye module is used to permit several actions to proceed concurrently by generating simultaneous ready/ acknowledge cycles on its output links.
5) The junction module causes an operation to wait for several independent events to occur.rt waits until a ready signal has been received on each of its input links before generating a ready/acknowledge cycle on its output link.
6) The trigger module implements the basic control mechanism for an operator in a chain of opeators that processes data in pipeline fashion.It generates a ready/ acknowledge cycle (the stage operations) when a ready signal is received, provided that the next stage is idle (the acknowledge signal of the current stage is used as the ready signal for the next stage).
7) The decision module permits actions by a control structure to be affected by external conditions.When a ready signal is received, it performs a test, and depending on the result a ready/acknowledge cycle is generated on one of its output links.
8) The union module causes a ready/acknowledge cycle to occur on its output link for a ready signal on any of its input links.
9) The arbiter module causes a ready/acknowledge cycle on one of the output links for each ready/acknowledge cycle in the corresponding input links.It provides an interlocking mechanism so that only one of a set of activities can be executed at a time.
It should be emphasized that none of the languages 14.2 uses ready/acknowledgement signals.The important fact is that the behavior of networks built out of MIT modules can be described with more or less ease by programs written in the different languages.Control signal proto- cols are an implementation issue and not a language primitive.This is the proper attitude, otherwise the languages would be restricted to the description of systems implemented with a specific technology.
Table VII shows that the languages tend not to include primitives for the source and sink functions.This is due to their rather limited usefulness, dictated mostly by the control signal protocol.The lack of arbitration as a primitive presents a different issue.Either arbiters are useful only at higher levels than the RT level or language de- signers have overlooked the need for this facility.A case where it becomes useful is the description of the behavior of pipelined systems.

VII. BEHAVIORAL AND STRUCTURAL
DESCRIPTIONS Several levels of detail can be used in a system description.They range from behavioral descriptions (in which the properties of the system are specified in terms of the input/ output relationship between variables-a black box ap- proach), to stru6tural descriptions (where the system is described in terms of the real hardware components and their interconnections).Intermediate, functional, descrip- tions represent the system in terms of the actual com- ponents and their functional relationship or algorithm.
The distinction between these different levels might not be clear at times.Our definition does not attempt to set standards but rather to appeal to an intuitive distinction between what a system does and how it is built.
Behavioral descriptions are closer to conventional pro- grams in most programming languages.Complex expres- sions and operators are allowed for simplicity in the description, e.g., the use of arithmetic expressions as subscripts.Variables and operators do not necessarily have a hardware counterpart and timing details are usually ignored, i.e., operations are assumed to take no time since the intention is only to show the algorithm in terms of input/output functions.
Functional descriptions are closer to the real hardware.They describe the system as an algorithm in terms of the real registers and components of the machine.The opera- tors may or may not be hardware primitives and expres- sions can be of a complicated nature.Timing and con- currency are taken into account.
Structural descriptions represent the system in terms of the hardware components.Operators have physical counterparts (i.e., they are primitive) and the descrip- tion-s tend to give more detail than the other two levels.Being closer to the physical implementation, timing is described in terms of clock pulses or event completed signals.
Nonprocedural languages tend to impose more restric- tions on the user.The sequence of operations (the algo- rithm) must be described by providing the timing and the (2) Conjunction of signals as condition in conditional statements.
(4) Output of decoder/counter network as control expression (label) conditions to execute the operations.This kind of detail is irrelevant if the designer only wants to describe the algorithm in terms of input/output sequences, without any consideration to the actual clock pulses or state register values.
Procedural languages are better suited for behavorial descriptions.The algorithm is described as a sequence of steps (as in conventional programming languages) and the details of control can be ignored.At the lower level, where these details (required by nonprocedural languages) are needed, procedural languages are capable of describing the system using conditional statements.The conditions are the labels used in nonprocedural languages.In fact, at the lower levels, if necessary, a procedural description can appear as a table of (concurrent) primitive conditional actions, much like a nonprocedural description.

A. Instruction Set Processors
The behavior of a processor is determined by the nature and sequence of its operations.This sequence is given by a set of bits in primary memory (a program) and a set of interpretation rules (usually in the central processor).Thus, if we specify the nature of the operations and the rules of interpretation, the actual behavior of the processor depends on the initial conditions and the particular pro- gram.
This behavioral level describes, roughly speaking, what the programmer sees, namely, the architecture of the machine.
Computer architectures are usually described in terms of the following relatively fixed format.
Memory: Physical components which hold information encoded in data.
Primary-Memory: Contains program and its data.
Processor-State: Registers accessible to the program, i.e., general registers and program location counter.
Console-State: Lights and switches enabling communication with the processor.
Input/Output-State: Controller registers accessible to the program.Data-Types: Described in terms of registers which could carry information.
Data-Operations: Defining operations that can be carried out in terms of data-types.
Instruction-Format: Specific instances of data-types.
Addressing-Scheme: Defining how instructions and data are accessed.
Interpreter: The mechanism of the processor which fetches, decodes, and executes the instructions.
Instruction-Set: Definition of the particular instructions that the processor executes.
The structural description, on the other hand, corres- ponds to the machine organization, i.e., the particular combination of registers, busses, combinational networks, and control (whether microprogramming or sequential).
The selection of an architecture is usually the first step in the design process, and it is followed by the selection of a machine organization.This process, however, is not a top down set of decisions.The architecture influences the machine organization by impossing a set of requirements (a particular instruction set) and the organization, mainly for technological reasons, influences the archi- tecture of the machine.The result is usually that a given computer architecture can be implemented on a set of machine organizations, and a given organization accepts several architectures.
B. Organization of the Description CDL: The description consists of a list of declaration statements followed by a list of execution statements.There is no provision for partition of tha -description in blocks of related statements (reflecting a particular or- ganization or hierarchy of activities).
APDL: The description is organized like an Algol pro- gram, i.e., a set of blocks, each with its own declarations and statements.Blocks can be nested to any depth, pro- viding a simple scheme to organize a description in a hierarchical fashion.
APL: The programs are sequences of statements (there are no declarations in the language).Large programs can be divided in segments or functions.Alert descriptions are organized in microprograms.A description consists of a list of declarations followed by a list of microprograms.
ISP: Descriptions follow the block structure of Algol programs.A description of a machine consists of a list of declarations followed by the processes (subunits) and action sequences.Descriptions can be named and used as independant processes or as part of larger units.

C. Example: A Microprogram-Controlled Computer
A small microprogrammed computer [L07] will be described in CDL (the original description) and in ISP (at different levels).The purpose of the example is to show how a description can be organized to depict different levels of detail.
The processor has a main memory M with capacity of 32K, 24 bit words, and a control memory of 1K, 24 bit words.
The microprograms reside in the control memory and the sequencing of microinstructions is explicitly given in an address field (the first 10 bits) in each microword.This address points to the next microinstruction to be executed.
The microwords contain, besides the address of the successor, several one bit fields, each representing a spe- cific microorder.The microorders in a microword are executed in synchronism with a three phase clock.
Instructions are fetched and executed using two control memory words.The first one implements the instruction fetch and the second implements the instruction proper, i.e., the data operations.For this simple machine each instruction requires only one microword.An instruction cycle of the machine, takes 6 clock pulses (3 for each control memory word).The address of the first control memory word (the fetch sequence) is a constant (9).The address of the second (the instruction sequence) is given by the operation code.F(10) to a physical representation, with the constraint that both representations define the same behavior (algorithm) and that the physical implementation satisfies the constraints associated with the elements (e.g., fan-in, fan-out, etc.) and constraints imposed by the designer (cost, speed, etc.).This application has been relatively successful at the lower levels of design (combinational and sequential switching circuits).
As the complexity and size of the systems increases, modular components have become a necessity for the designer.It is no longer economical (in terms of design and development time) to design at the gate level.Several sets of modules are available [EMO1- [Mll].They reflect in hardware -(the physical representation) what the RT languages are for the symbolic representation of systems, namely, reduction of the complexity of the design task by abstraction and elimination of redundant details.
At this level, automatic design programs have yet to be implemented.There are no techniques for analysis or synthesis4 of modular digital systems, but this situation is bound to change as more research is done in the area [R01].
For a survey on the automated design and analysis of digital systems at the gate level of design, see [S02].
CDL: A simulator and a Boolean translator have been implemented for CDL [S12].During the execution of the simulator, the contents of chosen registers, memory words, and positions of switches can be displayed at every clock cycle.The execution of the simulator runs in a loop called label cycle, during which: 1) If a manual switch operation occurs, the micro- statements of the corresponding switch statement are carried out.
2) All labels are evaluated, the activated lables, i.e., the labels having the value 1, are located.
3) The microstatements of the activated labels are carried out in two steps.First, all values to be stored in various registers and memories are evaluated and collected.Then the collected values are stored.
4) It is checked whether the simulation should be ter- minated.If not, the process starts from 1 again.
The translation into Boolean equations consists of four phases.During the first.phase, the design is scanned and a microstatement table is generated.The second phase generates a truth table for each microstatement.During the third phase, Boolean product terms are generated from the truth tables.The fourth phase sorts and com- bines the product terms into a list of Boolean input equations for each device.Since the meaning of the inputs to the storage devices depend on the type of device (flip-flop), Simulation of modular systems has been more successful, perhaps because of the closeness of the RT level description to conventional programming.This allows simple transliteration of the RT descrip- tion into executable programs, providing cheap and fast simulation (although in many cases, RT languages.are compiled directly).Most simulation techniques used at the gate level are applicable to register transfer systems.the output of the Boolean translator must be processed later with given flip-flop definitions.
APDL: An APDL system exists, in which descriptions are compiled into executable code.5This code, combined with a set of run time routines, can be executed to simulate the system described.Since APDL has no simulation command language, all reading of data, computing of statistics, and printing of results must be included as part of the description.
A special procedure "T" (Time) is called, at run time, at the beginning of each simulated cycle time.This pro- cedure increases the cycle time counter, rests the Pulse variables that were true during the previous cycle time, and evaluates the If Ever conditions (executing the proper statements if the condition is satisfied).At the end of the procedure, control is returned to the object code program and the nonmonitoring statements of the time block are executed.
The implementation program produces a hardware specification list consisting of three items.
1) A list of hardware components.
2) A list of data paths between the hardware elements.
3) An SFD-Algol [L19] description of a finite state controller that will sequence the data transfers via the data paths listed in 2).The hardware specification is not complete since it does not provide the information on the particular types of elements to be used, i.e., they are somewhat idealized but have feasible realization.
APL: The ALERT implementation does not provide a simulation capability.The system is used as a front end for the IBM Design and Logic Automation Systems [S04], [S18].The description is processed in 8 steps that provide details needed to complete the logic design.
1) Translation: Transforms the description into an in- ternal format, performing syntax analysis.
4) Sequence Analysis: Control and sequencing requirements are determined.
5) Flip-Flop Identification: Nondeclared variables are implemented as flip-flops whenever a memory capability is required.
6) Control Provision: Introduces the sequence control counters.
7) Consolidation: Eliminates redundant logic blocks, rearranges the connections, and associated elements are tied together.
8) Expansion: Arrays of elements are replaced by in- dividual devices and connections.
ISP: No general purpose ISP compiler is available.An ISP translator into a flowchart notation, for a particular set of building blocks (DEC PDP-16), has been imple- mented at CMU.A wiring list generator for the same application is currently under design.
IX. LANGUAGE REQUIREMENTS What properties are desired in a language for writing behavioral and structural descriptions of a digital system?
We can divide the set of properties in two classes: one of them consists of the requirements for a scientific notation used in a design process; and the other has to deal directly with the objects we are devising, namely digital systems, particularly computers.

General Properties
1) Readability: The notation is going to be used as a conveyor of information, not only between man and ma- chines but among humans, who do not all have the same experience or involvement in the design.A description in this notation should be precise, concise, and elegant (con- siderations of typography, character sets, formats, the way operations such as array accesses are described, etc.).It should be usable as the ultimate source of information about the object.Information should be extracted from the context rather than by syntax which clouds the description (e.g.', register declarations, keywords, etc.)  APL's compact encoding of algorithms ("one-liners") together with the right to left precedence of operators require the evelopment of some reading skills.Block structures in APDL and ISP permit the partition of the' description thus making it more useful as a design docu- ment.CDL's small character set imposes restrictions, such as the use of "-" as both a range operator and a register concatenation operator.APL and ISP require large character sets and many symbols have to be trans- literated in order to use a conventional computer character set.APDL requires a large number of re- served keywords.
2) Familiarity: Primitive concepts in the language should be named and used in a way consistent with general practice.
CDL, APDL, and ISP were designed specifically to describe digital systems.APL suffers from the use of a nonconventional precedence.
3) Generality: The notation should describe the elements occurring in the universe of interest, and at several levels of detail (in a hierarchical way), by suppressing repetitive or unnecessary detail.
APDL and ISP, due to their block structure, allow descriptions at different levels of detail.CDL some- times requires more detail than necessary (e.g., the explicit use of the memory address register in memory access operations).APL with its powerful set of opera- tors can be used to describe algorithms at different levels of detail.
4) Simplicity: There should be few primitive concepts, and they should be used consistently throughout the description, avoiding special cases of more general con- cepts, or things that are of relative importance or that imply a specific implementation.APL is by far the simplest language.It uses very few constructs.CDL and ISP are similar in complexity (CDL uses several types of declarations as oppossed to the generalized carrier declaration of ISP).APDL uses too many types of registers and arrays which are special cases of the general concept of information carriers.

Specific Properties
1) Extentsibility: The language should be able to extend gracefully by defining constructs in terms of elements already in the language.This also gives the capability to describe machines in a hierarchical fashion.
None of the language provides a real set of extension facilities (i.e., mechanisms that allow the modificatiion or amplification of the syntax or semantics of language constructs).The languages are limited to the definition of new operators (combinational or sequential) as sub- routines (open and close).
2) Fidelity: The organization of the description should reflect the organization of the machine, making the inten- tions of the designers transparent to the users, humans or simulation/production automation processes.
ISP and APDL provide more flexibility in the organiza- tion and partition of the diescription to reflect the ma- chine organization at different levels depending on the user.CDL stays closer to the organization of the ma- chine at the RT level and it is not as good at the pro- gramming level.The lack of block structure and paral- lelism in APL presents a major problem.Additional conventions must be added as in ALERT.
3) Timing and Concurrency: Machines are essentially parallel and this implies that concurrency should be the rule rather than the exception.
All hardware design languages allow the description of parallel actions.APDL time blocks describing parallel activities can not be nested.ALERT provides some conventions to handle timiing and concurrent activities (user provided versus system provided control).4) Syntactically Simple (Writable): The notation is a tool for designers and descriptions should be written by them and not (necessarily) by programmers.
Hardware description languages tend to be good in this respect.APDL, being based on a richer language (Algol 60), may require more programming skills.
5) Hardware Independence: The notation should be rela- tively independent of any hardware technology, machine organization, timing mode, design procedure, or simu- lation/production techniques.This is somewhat in conflict wvith the fidelity property.
The languages surveyed provide relatively good hard- ware independence.CDL and APDL are best suited for synchronous systems (CDL uses explicit clocks; APDL uses an implicit system clock to sequence the time blocks).The Alert implementation of APL is oriented towards a specific technology (IBM's SLT).ISP is oriented towards asynchronous systems (the semantics of the Next operator would have to be extended to represent synchronous systems).
6) Separability: The notation should be able to express the dichotomy between data and control.It should express the structure and behavior of the data flow, which implies the behavior of the control part.Also separability should permit the function of a primitive (e.g., an AND gate) to be described in an independent fashion.
CDL (as all non procedural languages) tends to be better in this respect.ISP could benefit from the addi- tion of specialized control components like clocks and pulses.Algol statements in APDL mix data and control operations.The separability in this case is provided by the compiler.The same problem appears in APL.The Alert system provides a default control mechanism (a decoder/counter pair).
X. CONCLUSIONS A conclusion that might be extracted from the preceding comparison is that, the languages do all that could be desired, except for minor blemishes.This is, however, not true.Users of these languages tend to write descriptions in terms of very simple constructs, because that is all that the languages provide.Similarly, and to complete the circular argument, these languages are designed with simple elements because that is all the users need.In fact, the use of these languages for design is centered around academic environments and they are rarely, if at all, used in industry.The situation will change in the future, as the level at which we design computer systems raises.
We can think of some areas of application for which better hardware description languages are needed.The proliferation of microprogramming systems increases the number of instruction set processors that can be imple- mented.Since a fixed organization (the microcode inter- preter) can support several architectures we need a nota- tion that allows the description of the machine organiza- tion as well as the different instruction sets (architectures).The proliferation of machines introduces a problem in the production of software.Standard languages (Fortran, Cobol, etc.) have alleviated the problem with respect to the user side but there still remains the variability on the machine side.Compiler writing is an expensive task and automatic programming systems (compiler-compilers) have not taken into account this variability on the target machine.If we expect to solve the problem we need com- piler-compilers that accept as inputs both the language description (syntax and semantics) and the target ma- chine description.6None of the existing hardware design languages is useful in this problem and the issue is not just the production of code, but of "good" code and to do that, an automatic programming system must be able to extract, from the machine description, the synergetic effect of introduction sequences.
Many different applications of a hardware descriptive language can be subsumed under the term "documenta- tion", thus we have, 1) design and manufacturing docu- ments, 2) maintenance and verification documents, and 3) programming documents.
It is not clear whether a single language would be able to handle all these applications.If several languages are needed then they must interface smoothly to allow the generation of the documents to be an error-free (hopefully automated) process.If the interfaces between levels are not clean, the production of the different sets of documents becomes more difficult and the problem of verification across description levels must be solved.
The Department of Computer Science at Carnegie-Mellon University is currently conducting active research in the area of symbolic manipulation of machine descriptions.The nontraditional applications of RT languages mentioned above are only part of the applications being studied at CMU. [2], [3].Due to the large number of cells involved, this type of testing is very time consuming and costly.
The physical causes of failure in semiconductor memory are by no means fully understood They depend on such factors as component density, circuit layout, and method of manufacture.It has been found experimentally [2] that certain faults in various types of memory can be detected by applying standard test patterns to the memory.These tests attempt to check the READ and WRITE operation of each cell of the memory, under the assumption that the outcome of these operations may be sensitive to the data stored in certain cells of the memory.Thus they try to detect faults that are pattern sensitive and so are referred to as pattern-sensitivity tests.
A representative pattern-sensitivity test for a memory is the following "walking 1/0" test [4].The content of every cell in the memory is reset to 0. A 1 is written into the first memory cell C0.Then all cells in the memory are read in a prescribed sequence and verified.Next a 1 is written into the second memory location C,, and again every cell in the memory is checked.This operation is continued until the memory is filled with l's.The entire procedure is now repeated, this time writing a 0 into suc- cessive memory locations.If the memory contains r cells, then approximately 2r2 + 3r READ and WRITE operations are required.
The walking 1/0 test checks each memory cell for sensi- tivity to certain data stored in every other cell of the = M(0-32767,0-23), maini mernory CM (Hl) = CM (O -1023,0 -23), control memory Power (ON), Start (ON), Stop (ON), POi -3), three phase clock G*-O, F-0, H<-O, C4-0, D*-O, R*-O, G*.1, F(12)*-v, F(O-11,13-22)4-0, G 0,-O greatly increased the use of semi- conductor random-access memories in computer main- frames[1].These memories are usually large-scale inte- grated circuit devices and employ either bipolar or MOS techniques.Extensive functional testing of semiconductor memories is carried out by both users and manufacturers Manuscript received February 28, 1974; revised August 19, 1974.This work was supported by the National Science Foundation under Grant GK-37455 and by the Joint Services Electronics Program under Contract F44620-71-C-0067.The author is with the Department of Electrical Engineering and the Computer Science Program, University of Southern California, Los Angeles, Calif.90007.

TABLE VI SEEQUENCING
IN PROCEDURAL LANGUAGE