Data supporting figures and tables in Reimagining Electrical Diagrams in Construction: Automated Symbol Detection and Wiring Design and Generation with Deep Learning

<h3><b>Overview</b></h3><p dir="ltr">This dataset supports the findings of the research titled <i>“Reimagining Electrical Diagrams in Construction: Automated Symbol Detection and Wiring Design and Generation with Deep Learning.”</i><br>The study presents a fully automated framework that digitises complex electrical diagrams through two main components:</p><ol><li><b>Symbol Recognition:</b> A YOLOv8-based deep learning model trained to recognise 30 electrical symbol classes in industrial diagrams.</li><li><b>Automated Wiring Design:</b> A modified A* pathfinding algorithm that generates orthogonal wiring between recognised symbols, reducing total wire length by 44% compared to traditional methods.</li></ol><p dir="ltr">The dataset includes preprocessing experiments such as <b>data augmentation (AUG)</b> and <b>low-intensity sampling (LINS)</b> to improve detection performance and mitigate class imbalance.</p><h3><b>Datasets Included</b></h3><p dir="ltr">This data bundle contains the primary files used to produce figures and tables within the manuscript, including:</p><ul><li><b>Symbol distribution and augmentation statistics</b> (Table 1).</li><li><b>Model performance metrics across preprocessing experiments (YOLOv7 and YOLOv8)</b> (Tables 3–5).</li><li><b>Wiring algorithm evaluation results</b> comparing the multiline plotter and modified A* methods (Table 6).</li><li><b>Hardware and software configuration details</b> (Table 2).</li><li><b>Examples of detected symbols, wiring paths, and recognition visualisations</b> (Figures 1–7).</li></ul><p dir="ltr">Each table is provided in CSV format, mapping data files directly to their corresponding figure or table in the paper.</p><h3><b>Use Cases</b></h3><p dir="ltr">This dataset can be used for:</p><ul><li>Benchmarking YOLO-based models for electrical symbol recognition in high-resolution engineering diagrams.</li><li>Studying the impact of class imbalance, augmentation, and preprocessing techniques on detection accuracy.</li><li>Evaluating automated wiring algorithms using modified A* search for layout optimisation.</li><li>Reproducing experimental setups for symbol recognition and routing in industrial diagram analysis.</li></ul><p></p>