Image Fusion with multiple image sources has now a day’s been very popular in many fields such as medical imaging, computer vision, paintings, remote sensing, and in many applications. To get an image with sharp and crisp, image fusion technique is used in which two or more images are combined to get an image with more details from the same source images. The implementation of VLSI architecture for efficient 2-D DWT and inverse 2-DWT processor is required, that consumes less area, memory efficient and should operate with a high frequency to use in real-time applications. The implementation of lifting based scheme (DWT) requires less arithmetic complex, less memory and can be implement in parallel. Huang et al.,[7] introduced a flipping structure which provides a critical path of Tm+Ta. Now there is a requirement to improve memory efficiency. Various parallel architectures were proposed for lifting based 2-D DWT. Y.Hu et al.,[5] proposed a modified strip based scanning and parallel architecture for 2-D DWT. The on-chip memory for this is 3N+24P of image with P parallel Processing Units (PU). The architecture designed for 2-D IDWT is similar to that of 2-D DWT but the operation takes place in reverse direction. So the same architecture is implemented using LABVIEW software and the results can be obtained
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