Exploring EPC Gen-2 clock generation with self-calibrating oscillator

This works presents a study that aims the development

of a power efficient clock generator to fulfill EPCglobal

class 1 generation 2 RFID standard specification. Firstly, clock frequency requirements were investigated. Then, the standard characteristics were explored in order to define a self-calibration methodology. The circuit designed was simulated at electric device level in a 0.18 micrometer CMOS technology. Power consumption results presented (117 nW/MHz in oscillator) proved the feasibility of this strategy. The tolerance to process variation and temperature fluctuation were verified by simulation.